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DP83TC814R-Q1: Poor/Intermittent Communication Quality with DP83TC814R-Q1

wang hongbo
Prodigy 10 points
Part Number: DP83TC814R-Q1
Other Parts Discussed in Thread: DP83TC814S-Q1

Issue Description:
During testing with two identical boards using the same hardware and software configuration for the PHY, one PHY was configured as Slave and the other as Master. We observed that on some boards, the Ethernet communication quality is very poor.

The communication between the controller and the PHY uses the RGMII interface for data transmission. When comparing register data between normal and abnormal boards, we found that the SGMII_STATUS register's link_status_1000b field reads 1 on normal boards, but 0 on boards with poor communication.

Waveform measurements of data and clock signals on normal and abnormal boards show similar characteristics.

The key question is:
Since we are using the RGMII interface and not SGMII, why does the SGMII_STATUS register show a value of 1 on normal boards?

  • +1
    TI__Expert 5240 points

    Hi Wang,

    Can you please share a schematic of the device set-up? Could you also share signal quality difference between the normal and abnormal boards? If you are using the DP83TC814R-Q1, it does not have SGMII support. The SGMII link status bit being set could potentially be caused by a bootstrapping issue, so it will be useful to see that configuration.

    Best regards,

    Greg

  • 0
    Prodigy 10 points

    Hi Greg

    We have identified the issue: the poor Ethernet quality of the abnormal board was caused by an incorrect clock phase in the transmitted signal. Modifying the relevant parameters resolved this problem. However, is the DP83TC814R-Q1 actually not compatible with SGMII? If this bit is set to 1, could it be due to abnormal bootstrapping?

    I would like to express my sincere gratitude for your invaluable assistance.

  • 0 in reply to wang hongbo
    TI__Expert 5240 points

    Hi Wang,

    Thank you for the update. The DP83TC814R-Q1 does not support SGMII, while DP83TC814S-Q1 does support SGMII. These devices share the same data sheet, but the SGMII_STATUS register is not valid for the DP83TC814R-Q1 device. The bit you noticed being set likely does not affect the device function. I can check over your bootstrapping to ensure there are no abnormalities there, just in case.

    Best regards,

    Greg