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DP83826AI: Packet alignment and preamble length

Dom
Prodigy 10 points

Part Number: DP83826AI

Dear support team, 

the microcontroller we're planning to use has an Ethernet MAC with specific requirements regarding the packet alingment and preamble length, limiting the number of interoperable PHYs. 

In 10 MBit mode the MAC requires the packet to be octet-aligned. It cannot handle packets correctly if the preamble has been shortened, leaving the packet non-octet-aligned. Also it requires a preamble length of at least 1 byte. 

Does the DP83826A PHY comply with these requirements? 

Thank you

  • 0
    TI__Mastermind 23141 points

    Hi Dominik, 

    In 10M, the PHY may consume the preamble for the timing lock, but the PHY will pad the consumed preamble so the MAC should not see any change on the preamble length. I believe the PHY will be compliant to the MCU's requirement. 

    Please let me know your thoughts. 

    Best,
    J

  • 0 in reply to J
    Prodigy 10 points

    Hi J, 

    thanks for the quick response. So it should be compatible but there remains an uncertainty. I guess we'll have to give it a try with a prototype. 

    Thank you, best regards

    Dominik