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TAS2505EVM: Issue with TAS2505EVM I²S Signals When Using External Master

Part Number: TAS2505EVM
Other Parts Discussed in Thread: TAS2505

Setup Detail

We are using the TAS2505EVM for our proof-of-concept.
When the EVM runs in standalone mode, everything works correctly.

However, when we connect an external I²S master to drive the TAS2505, the signals at the TAS2505 side do not appear correct.

Hardware Setup

  • IOVDD = 3.3 V

  • To isolate onboard signals:

    • W8 and W9 jumpers removed to isolate BCLK and DIN

    • BCLK and DIN connected via pin-2 of W8 and W9 to Extrenal Master.

  • There is no isolation jumper for WCLK, so the external WCLK is wired directly from the WCLK test point to External master.

  • I²C is connected from W2 and W3 to external master.

  • External master configures the TAS2505 over I²C
    -- Verify Page 0 Registers --
    PG0[0x04] = 0x0A
    PG0[0x0B] = 0x81
    PG0[0x0C] = 0x81
    PG0[0x0D] = 0x00
    PG0[0x0E] = 0x40
    PG0[0x1B] = 0x00
    PG0[0x3F] = 0x90
    PG0[0x40] = 0x04
    PG0[0x41] = 0x00

    -- Verify Page 1 Registers --
    PG1[0x02] = 0x04
    PG1[0x0C] = 0x08
    PG1[0x09] = 0x20
    PG1[0x16] = 0x00
    === TAS2505 HP Ready === 

    Query

    After completing configuration and applying external I²S signals:

    Observed at TAS2505 Pins

    • BCLK

      • Correct 3.3 V logic level

    • WCLK

      • Logic level drops to ~600 mV instead of 3.3 V

    • DIN

      • No valid data

      • Only noise of 1-10 mV during data transmission

    Question

    What could be causing:

    1. The reduced WCLK logic level (600 mV instead of 3.3 V)?

    2. The absence of valid DIN signal at the TAS2505 input?

  • Hi Shivam,

    Have you verified a good GND connection for each digital signal? Sometimes that is overlooked.

    From the register configuration, I noticed that input clock is set for GPIO (PG0[0x04] = 0x0A). Are you actually feeding a clock to this pin? What is the frequency?
    Not sure if the wrong clock configuration could affect WCLK and DIN in that way though, but still worth to check.

    Regarding WCLK signal, you'll have to cut the trace on EVM to disconnect from the onboard processor. Otherwise, the onboard signal will collide with the external one.

    Best regards,
    -Ivan Salazar
    Applications Engineer