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Original question:

SN65HVD23: Long Cable Length

SN65HVD23: SN65HVD23 avoiding test mode

Brewster LaMacchia
Prodigy 10 points
Part Number: SN65HVD23
Other Parts Discussed in Thread: SN65HVD21, SN65HVD24, SN65HVD20, RS485-HF-DPLX-EVM

Hi,

Looking to use the SN65HVD23 in an application where continuous data is being sent unidirectionally through up to 200m of shielded twisted pair at up to 10 Mbit/sec.  Page 21 of the datasheet, section 10.4.1 Test Mode Driver Disable, states:

If the input signal to the D pin is such that:
1. the signal has signaling rate above 4 Mbps (for the SN65HVD21 and SN65HVD24),
2. the signal has signaling rate above 6 Mbps (for the SN65HVD20 and SN65HVD23),
3. the signal has average amplitude from 1.2 V to 1.6 V (1.4 V +/- 200 mV), or
4. the average signal amplitude remains in this range for 100 us or longer,

The input D pin will be connected to a FPGA where Vhigh-Vlow/2 would be around 1.3V and the waveform (from a serializer) can be expected to average a 50% duty cycle.  Data is sent continuously.

In initial testing of the part (using a pair of RS485-HF-DPLX-EVM) and a 10 MHz 50% duty cycle clock output failure due to test mode was not observed, but also may have not noticed occasional dropouts.

Subsequent testing used a 3 Mbit/sec rate as the initial system design will use that rate.  A future upgrade will increase that about three times, hence the 10 Mbit/sec design allowance.

If I've read the section 10.4.1 description correctly then the SN65HVD23 can't be used above 6 Mbps even though the product description says it supports up to 25 Mbps.

If 10.4.1. is correct and the part is limited to 6 Mbps due to the test mode is there a part that can support 200m of cable at 10 Mbps? Or is there some way to prevent entering test mode under the operating conditions we have? Figure 11-2 shows the part running at 25 Mbps so I'm hoping I have misunderstood what 10.4.1 is saying.

Thanks,

Brewster

  • 0
    TI__Guru* 77221 points

    Hi Brewster,

    Do you have the top markings for the device that you ended up testing? 

    This device went through a redesign and my guess is that the new die probably didn't design in the test mode. 

    -Bobby

  • 0 in reply to BOBBY
    Prodigy 10 points

    Hi Bobby,  


    Thanks for the speedy reply. I'm out of the office today but will check the parts on Monday. 

    I poked around but didn't see any product change notifications for the part?  Pretty sure the project will end up using the part and would want to give purchasing any date code/batch restrictions just in case they found a "good deal" on some old parts.

    Brewster

  • +1 in reply to Brewster LaMacchia
    TI__Guru* 77221 points

    Hi Brewster,

    This is the PCN that issued that calls out the new design/die. 

    SN65HVD2x PCN20220926001.1.pdf

    If you have the original sticker that the devices came in, you can 'CSO' for the device came from. Line 20L if it is RFB it is the new die. If the line states DLN then it is the old die (with the test mode). This would be the best way to verify which one you have.

    -Bobby

  • 0 in reply to BOBBY
    Prodigy 10 points

    Hi Bobby,

    Sorry for the delayed response.  The SMT parts I received have CSO:RFB and were used on the TI EVM kits.

    I also got some older PDIP parts as we wired up a could of protoboards to further test things.

    Though now that I think about it I'm not sure I ran the PDIP parts 10 Mbps as the initial proof of concept was at 3 Mbps and we had tested the EVMs at 10 Mbps.

    The PCN references datasheet Rev G and Rev G still talks about the test mode.  Should that be removed from the datasheet?

    Thanks again for the guidance and have a great holiday.

    Brewster