DS90UB960-Q1: TI953+TI960 Sensor I2C ACK

Hi Xingxing,

Can you confirm you do not have auto ack all enabled on any of the ports on the UB960? This is set in register 0x58[5]. 

See the following on AUTO_ACK_ALL: AUTO_ACK_ALL bits in register 0x58 will respectively pass all addresses to the remote serializer I2C bus, regardless of valid I2C addresses defined in the deserializer, and acknowledge all remote I2C commands sent without waiting for a response from the connected serializer. 

Beyond this restriction, if targeting the correct address the device will pass through the ACK from the sensor. After confirming auto ack all is not enabled, we can proceed further. 

To proceed, would you be able to provide a block diagram of your system along with initialization script highlights the I2C transactions of concern here? 

Best,

Zoe

Hi Zoe,

Here is serdes setting. And one ti960 deserialzier connecting four ti953 serializars. 

#ifndef __UB9XX_H__
#define __UB9XX_H__

struct ub9xx_reg {
u8 slave_addr;
u8 reg;
u8 val;
};

#define UB9XX_DELAY 0x00

static struct ub9xx_reg ub9xx_yuv_1600M_0[] = {
{0x30,0x4C,0x01}, // select RX port 0
// auto ACK setup
{0x30,0x5B,0x31}, // set serializer address with freeze
{0x30,0x5C,0x11}, // set SER alias and auto ACK
{0x30,0x58,0x7A}, // Enable I2C passthrough with auto ACK, BC rate = 10Mbps
// 953 configs
{0x08,0x01,0x03}, //reset UB953
{UB9XX_DELAY, 0x00, 20}, // delay 20 msec
{0x08,0x0B,0x1C}, //400K i2c speed
{0x08,0x0C,0x1C},
{0x08,0x02,0x73}, // continuous clock, 4 lanes
{0x08,0x0E,0xF0}, // disable 935 GPIO0 input and enable output
{0x08,0x0D,0x10}, // Enable remote Des GPIO0 data on local GPIO0; Pull down gpio2(ISP RESET)
{UB9XX_DELAY, 0x00, 10}, //delay 10 msec
{0x08,0x0D,0x14}, //reset AP1302
{0x08,0x03,0x12}, // MODE override async external clock
{0x08,0x01,0x01}, // soft reset
{UB9XX_DELAY, 0x00, 10}, //delay 10 msec
// I2C address and alias setup
{0x30,0x58,0x5A}, // Disable auto ACK
{0x30,0x5B,0x30}, // remove freeze
{0x30,0x5C,0x10}, // disable auto ACK
{0x30,0x5D,0x20}, // configure imager address
{0x30,0x65,0x20}, // configure imager alias
{0x30,0x5E,0x78}, // configure ISP address
{0x30,0x66,0x40}, // configure ISP alias
// 960 config
{0x30,0x6D,0x7C}, // FPD3 CSI-2 input mode
{0x30,0x6E,0x8A}, // map Fsync signal to 953 GPIO0 output
{0x30,0x72,0}, // map VC-ID to 0

// FrameSync: 27Hz, 10%/90% duty cycle
{0x30,0x19,0x04}, // FS_HIGH_TIME_1
{0x30,0x1A,0x66}, // FS_HIGH_TIME_0
{0x30,0x1B,0x2B}, // FS_LOW_TIME_1 27fps
{0x30,0x1C,0xDF}, // FS_LOW_TIME_0 27fps
{0x30,0x18,0x01}, // enable internally generated FrameSync
{UB9XX_DELAY, 0x00, 100},
// CSI Output / Forwarding Config
{0x30,0x1F,0x00}, // 1.472 - 1.664Gbps serial rate
{0x30,0x32,0x01}, // select CSI port 0
{0x30,0x34,0x31}, // enable skew
{0x30,0x33,0x43}, // enable skew cal, 4 lanes, continuous clock, enable CSI output
{0x30,0x21,0x03}, // basic sync forwarding on CSI port 0
{0x30,0x20,0x00}, // forward all RX port to CSI port 0, enable forwarding
};

static struct ub9xx_reg ub9xx_yuv_1600M_1[] = {
{0x30,0x4C,0x12}, // select RX port 1
// auto ACK setup
{0x30,0x5B,0x31}, // set serializer address with freeze
{0x30,0x5C,0x13}, // set SER alias and auto ACK
{0x30,0x58,0x7A}, // Enable I2C passthrough with auto ACK, BC rate = 10Mbps
// 953 config
{0x09,0x01,0x03}, //reset UB953
{UB9XX_DELAY, 0x00, 20}, // delay 20 msec
{0x09,0x0B,0x1C}, //400K i2c speed
{0x09,0x0C,0x1C},
{0x09,0x02,0x73}, // continuous clock, 4 lanes
{0x09,0x0E,0xF0}, // disable 935 GPIO0 input and enable output
{0x09,0x0D,0x10}, // Enable remote Des GPIO0 data on local GPIO0; Pull down gpio2(ISP RESET)
{UB9XX_DELAY, 0x00, 10}, //delay 10 msec
{0x09,0x0D,0x14}, //reset AP1302
{0x09,0x03,0x12}, // MODE override async external clock
{0x09,0x01,0x01}, // soft reset
{UB9XX_DELAY, 0x00, 10},
// I2C address and alias setup
{0x30,0x58,0x5A}, // Disable auto ACK
{0x30,0x5B,0x30}, // remove freeze
{0x30,0x5C,0x12}, // disable auto ACK
{0x30,0x5D,0x20}, // configure imager address
{0x30,0x65,0x22}, // configure imager alias
{0x30,0x5E,0x78}, // configure ISP address
{0x30,0x66,0x42}, // configure ISP alias
// 960 config
{0x30,0x6D,0x7C}, // FPD3 CSI-2 input mode
{0x30,0x6E,0x8A}, // map Fsync signal to 953 GPIO0 output
{0x30,0x72,1}, // map VC-ID to 1

// FrameSync: 27Hz, 10%/90% duty cycle
{0x30,0x19,0x04}, // FS_HIGH_TIME_1
{0x30,0x1A,0x66}, // FS_HIGH_TIME_0
{0x30,0x1B,0x2B}, // FS_LOW_TIME_1 27fps
{0x30,0x1C,0xDF}, // FS_LOW_TIME_0 27fps
{0x30,0x18,0x01}, // enable internally generated FrameSync
{UB9XX_DELAY, 0x00, 100},
// CSI Output / Forwarding Config
{0x30,0x1F,0x00}, // 1.472 - 1.664Gbps serial rate
{0x30,0x32,0x01}, // select CSI port 0
{0x30,0x34,0x31}, // enable skew
{0x30,0x33,0x43}, // enable skew cal, 4 lanes, continuous clock, enable CSI output
{0x30,0x21,0x03}, // basic sync forwarding on CSI port 0
{0x30,0x20,0x00}, // forward all RX port to CSI port 0, enable forwarding
};

static struct ub9xx_reg ub9xx_yuv_1600M_2[] = {
{0x30,0x4C,0x24}, // select RX port 2
// auto ACK setup
{0x30,0x5B,0x31}, // set serializer address with freeze
{0x30,0x5C,0x15}, // set SER alias and auto ACK
{0x30,0x58,0x7A}, // Enable I2C passthrough with auto ACK, BC rate = 10Mbps
// 953 config
{0x0A,0x01,0x03}, //reset UB953
{UB9XX_DELAY, 0x00, 20}, // delay 20 msec
{0x0A,0x0B,0x1C}, //400K i2c speed
{0x0A,0x0C,0x1C},
{0x0A,0x02,0x73}, // continuous clock, 4 lanes
{0x0A,0x0E,0xF0}, // disable 935 GPIO0 input and enable output
{0x0A,0x0D,0x10}, // Enable remote Des GPIO0 data on local GPIO0; Pull down gpio2(ISP RESET)
{UB9XX_DELAY, 0x00, 10}, //delay 10 msec
{0x0A,0x0D,0x14}, //reset AP1302
{0x0A,0x03,0x12}, // MODE override async external clock
{0x0A,0x01,0x01}, // soft reset
{UB9XX_DELAY, 0x00, 10},
// I2C address and alias setup
{0x30,0x58,0x5A}, // Disable auto ACK
{0x30,0x5B,0x30}, // remove freeze
{0x30,0x5C,0x14}, // disable auto ACK
{0x30,0x5D,0x20}, // configure imager address
{0x30,0x65,0x24}, // configure imager alias
{0x30,0x5E,0x78}, // configure ISP address
{0x30,0x66,0x44}, // configure ISP alias
// 960 config
{0x30,0x6D,0x7C}, // FPD3 CSI-2 input mode
{0x30,0x6E,0x8A}, // map Fsync signal to 953 GPIO0 output
{0x30,0x72,2}, // map VC-ID to 2

// FrameSync: 27Hz, 10%/90% duty cycle
{0x30,0x19,0x04}, // FS_HIGH_TIME_1
{0x30,0x1A,0x66}, // FS_HIGH_TIME_0
{0x30,0x1B,0x2B}, // FS_LOW_TIME_1 27fps
{0x30,0x1C,0xDF}, // FS_LOW_TIME_0 27fps
{0x30,0x18,0x01}, // enable internally generated FrameSync
{UB9XX_DELAY, 0x00, 100},
// CSI Output / Forwarding Config
{0x30,0x1F,0x00}, // 1.472 - 1.664Gbps serial rate
{0x30,0x32,0x01}, // select CSI port 0
{0x30,0x34,0x31}, // enable skew
{0x30,0x33,0x43}, // enable skew cal, 4 lanes, continuous clock, enable CSI output
{0x30,0x21,0x03}, // basic sync forwarding on CSI port 0
{0x30,0x20,0x00}, // forward all RX port to CSI port 0, enable forwarding
};

static struct ub9xx_reg ub9xx_yuv_1600M_3[] = {
{0x30,0x4C,0x38}, // select RX port 3
// auto ACK setup
{0x30,0x5B,0x31}, // set serializer address with freeze
{0x30,0x5C,0x17}, // set SER alias and auto ACK
{0x30,0x58,0x7A}, // Enable I2C passthrough with auto ACK, BC rate = 10Mbps
// 953 config
{0x0B,0x01,0x03}, //reset UB953
{UB9XX_DELAY, 0x00, 20}, // delay 20 msec
{0x0B,0x0B,0x1C}, //400K i2c speed
{0x0B,0x0C,0x1C},
{0x0B,0x02,0x73}, // continuous clock, 4 lanes
{0x0B,0x0E,0xF0}, // disable 935 GPIO0 input and enable output
{0x0B,0x0D,0x10}, // Enable remote Des GPIO0 data on local GPIO0; Pull down gpio2(ISP RESET)
{UB9XX_DELAY, 0x00, 10}, //delay 10 msec
{0x0B,0x0D,0x14}, //reset AP1302
{0x0B,0x03,0x12}, // MODE override async external clock
{0x0B,0x01,0x01}, // soft reset
{UB9XX_DELAY, 0x00, 10},
// I2C address and alias setup
{0x30,0x58,0x5A}, // Disable auto ACK
{0x30,0x5B,0x30}, // remove freeze
{0x30,0x5C,0x16}, // disable auto ACK
{0x30,0x5D,0x20}, // configure imager address
{0x30,0x65,0x26}, // configure imager alias
{0x30,0x5E,0x78}, // configure ISP address
{0x30,0x66,0x46}, // configure ISP alias
// 960 config
{0x30,0x6D,0x7C}, // FPD3 CSI-2 input mode
{0x30,0x6E,0x8A}, // map Fsync signal to 953 GPIO0 output
{0x30,0x72,3}, // map VC-ID to 3

// FrameSync: 27Hz, 10%/90% duty cycle
{0x30,0x19,0x04}, // FS_HIGH_TIME_1
{0x30,0x1A,0x66}, // FS_HIGH_TIME_0
{0x30,0x1B,0x2B}, // FS_LOW_TIME_1 27fps
{0x30,0x1C,0xDF}, // FS_LOW_TIME_0 27fps
{0x30,0x18,0x01}, // enable internally generated FrameSync
{UB9XX_DELAY, 0x00, 100},
// CSI Output / Forwarding Config
{0x30,0x1F,0x00}, // 1.472 - 1.664Gbps serial rate
{0x30,0x32,0x01}, // select CSI port 0
{0x30,0x34,0x31}, // enable skew
{0x30,0x33,0x43}, // enable skew cal, 4 lanes, continuous clock, enable CSI output
{0x30,0x21,0x03}, // basic sync forwarding on CSI port 0
{0x30,0x20,0x00}, // forward all RX port to CSI port 0, enable forwarding
};



#endif

Hi Zoe,

     Do you know if ti953 can configure i2c drive capability?

Thanks

Xingxing

We measure the i2c traffic using i2c logic analyzer on the ti960 i2c bus and ti953 i2c bus. 

TI960 I2C bus have probability not  ACK signal. But ti953 i2c bus always have no issue. 

{0x30,0x58,0x5A}, // Disable auto ACK

We disabled the auto ACK when accessing sensor i2c. Is there any debug register for debugging such ACK signal not route from ti953 to ti960 successfully? 

This is i2c traffic data from ti960 side. You can open it using Total phase data center v6.72. 

toTI

We use i2c 32bytes burst mode. sometime it failed arround 20+ bytes.

The 953 will set it's own I2C timings and can operate as the proxy master to send I2C transactions to the deserializer. 

There is an BC CRC error on the ti953 side. One point is our ti953 have no local  oscillator. 

Do you know which frequency should I choose? I tried 50M and 2.5M. The I2C failure becomes even worse.

Hello,

The team is out due to a public Holiday in the US. Responses will be delayed until Monday.

Thank you for your patience

Hi Hamzeh Jaradat,

    Thank you for your reply.

We still can see BC CRC error on the ti953 side and error counter increase obviously. 

We need TI help to give some advice about how to address BC CRC error. hardware or register setting?

Thanks

Xingxing

Hi Xingxing, 

The BC rate set in 0x58 is dependent on the operating mode. Since you are intending to operate in external clock mode, the BC rate should be set to 10Mbps. This is what you have set in the previous script provided.

xingxing gu said:

There is an BC CRC error on the ti953 side. One point is our ti953 have no local  oscillator. 

If there is no local oscillator on the 953 side - what mode are you intending to run in? The script state external clock mode on the 953. If you are configuring external clock mode, then you will be operating in internal AON mode due to the absence of a local oscillator. AON mode will also assume a 10MBps back channel rate. Synchronous mode uses the 50Mbps BC rate. 

xingxing gu said:

---> Will 953 buffer the i2c data from deserialzier? What is the buffer size if yes?

There is not a I2C buffer on the 953. The I2C controller from the SoC is supposed to support clock stretching for this purpose. 

In general, BC CRC errors are typically seen when there is a HW set-up issue, not software. Examples or causes are a violation of the channel spec at the BC rate (~5MHz in this case) or PoC noise over the link. 

The address with failing transactions is terminating due to the I2C watchdog timer as the duration of the transaction is much longer than the passing transactions. In general for the 953 serializers we recommend setting register 0x0A=0x12.

I have a few questions on this set-up: 

1. Can you please provide the schematics for the 953 cameras and 960 being used in this project?
2. What cables are currently being used? Have these cables been changed? 
3. Have S-parameter measurements been taken for the entire system? 

In the I2C transaction logs you sent, only one address is showing failing transactions. The address with the failing transactions is 0x21 7-bit which matches the ISP alias of 0x42 for the module on RX port 1. If the I2C transactions failing are exclusively targeting the ISP, I suggest swapping the camera modules and repeating the test to see if it follows the HW on the RX port 1 module. 

Best,

Zoe

Zoe Bison said:

There is not a I2C buffer on the 953. The I2C controller from the SoC is supposed to support clock stretching for this purpose. 

We changed the BC rate to 50Mbps. Looks like it is more stable now. 
1. Will share the schematics later.

2. We are using coaxial cable.

3. Do you have any document about how to measure the S-parameter?

4. Any side effect when changing the BC rate from 10Mbps to 50Mbps?

Thanks

Xingxing 

Hi Xingxing, 

xingxing gu said:

2. We are using coaxial cable.

What type and length? For example, DACAR-462 10m. We can discuss this more in depth with the S-parameter measurements. 

xingxing gu said:

3. Do you have any document about how to measure the S-parameter?

Providing over email, this document is NDA restricted. 

xingxing gu said:

4. Any side effect when changing the BC rate from 10Mbps to 50Mbps?

Async mode is not intended to operate with a BC rate of 50Mbps. We will need to operate in sync mode with this in mind and remove the serializer mode overrides in your script. Are you able to collect a register dump of the impacted serializer when this issue is observed and when it is not? 

Best,

Zoe

Hi Zoe,

    1. Double checking with cusomer about the cable length. From our lab test, we only use 0.5m length cable .

    2. Yes. we changed to sync mode for 50Mbps. I will dump all registers setting. And there is no BC CRC error when using 50Mbps.

Thanks

Xingxing

Hi Xingxing,

Thanks for the update, let me know if there are any additional questions in the meantime. 

Best,

Zoe

Hi Zoe,

      I'm still not fully understand why 50Mbps BC rate works more stable then 10Mbps BC rate. If it is hardware issue, Both rate should have similar failure rate.

Thanks

Xingxing

Hi Xingxing, 

Operating characteristics observed by the serializer change with the change in BC frequency. Examples of changing conditions are insertion loss & return loss on the channel, and PoC noise. Based on the schematic provided the devices are being brought up in sync mode and then was changed to async external clock mode. With the change in mode, the SerDes have different expectations for operation. We would need more information from your test set-up to conclude the cause of the CRC errors at the 10Mbps BC rate. 

Best,

Zoe