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TUSB1210: TUSB1210 Clock Signal Length Matching

Part Number: TUSB1210

I am currently implementing the TUSB1210BRHBR on my design as a USB 2.0 host. I was looking at the routing guidelines on Table 10-1 in the datasheet and saw different reccomendations for the clock signal routing that made me question the correct path forward. 

Screenshot 2025-12-17 101740.png

Screenshot 2025-12-17 101838.png

Table 10-1 Item 1.03 says that routing reccomendations are true for CLK, and ULPI signals which should be routed to equalized length. It is unclear to me if this is saying that the CLK needs to be length matched to the ULPI signals as well, or just that it should be routed first.

Table 10-1 Item 4.00 says that the USB clock should be routed with the minimum possible trace length. If Item 1.03 is saying to length match the clock to the ULPI signals, then these two statements conflict eachother.

Has anyone who has used this part before have any insight on what the correct routing method is?

Thanks in advance!

  • HI Michael:

      I don't  think there is a conflict .

       Keep  trace  length matched  as much as possible for  all ULPI signals including CLK.

       Keep min possible trace length  for all ULPI  signals  including CLK..

      What FPGA  customer is going to use?

    Best

    Brian