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DS90UB954-Q1: Query about UB954A MIPI Duplication Support

Danilo A.
Mastermind 34110 points

Part Number: DS90UB954-Q1

Hi Team,

Posting on behalf of our customer.

We have found in the UB954A datasheet that it supports the duplication of MIPI for parallel processing. For our parallel processing, we’re planning for the below architecture.

Plan A:

So we have few queries related to the same.

1. Does the above mentioned diagram will create any I2C conflicts?. Is it possible to assign the I2C address using Register settings. If so, please suggest possible values. Also, please suggest the possible I2C address via HW settings.

2. How much delay does the Intermediate Deser-Ser introduce in the MIPI path?

3. Can I use an MCU to configure the registers of Intermediate Deser-Ser chipsets, rather than depending on SoC1/SoC2?

Plan B:

We have also prepared another architecture, without using an MCU for the register configuration. Please refer to the 2nd diagram attached below.

So here also, we have similar queries, as mentioned earlier.

1. Does the above mentioned diagram will create any I2C conflicts?. Is it possible to assign the I2C address using Register settings. If so, please suggest possible values. Also, please suggest the possible I2C address via HW settings.

2. How much delay does the Intermediate Deser-Ser introduce in the MIPI path?

3. Can you suggest a register configuration sequence for the Serializer and Deserializers by avoiding possible register conflicts, if any

Could you please review the architecture and let us know whether the proposed design will work as expected, or if any additional changes are required? Your input during this architectural review phase is greatly appreciated. Also, kindly respond to the queries we have raised.

Regards,

Danilo

  • 0
    TI__Guru** 116930 points

    Hello Danilo,

    Does the camera with the UB913A already exists? Because the input of the 913A is shown as MIPI but this is not supported using the UB913A. For MIPI image sensor, it is recommended to use either the UB935 or the UB953, based on the imager data rate. 

  • 0 in reply to Hamzeh Jaradat
    Prodigy 40 points

    Hi  

    Thank you for your response.

    Yes. The Camera is having UB913A as Serializer.

    Does the UB913A accepts MIPI as Input or not?. Because we got this camera from one of our vendors.

    We would appreciate it if you could provide answers to the other queries as well.

    Regards

    Eric

  • 0 in reply to Eric Sonnabend
    TI__Guru** 116930 points

    Hi Eric,

    The UB913A SER has a parallel interface, not a MIPI.

    On the duplicators you better use the following:

    Danilo A. said:
    1. Does the above mentioned diagram will create any I2C conflicts?. Is it possible to assign the I2C address using Register settings. If so, please suggest possible values. Also, please suggest the possible I2C address via HW settings.

    No I2C conflict since the addresses are different.

    Possible hardware settings are listed in the datasheet.

    Possible values via software settings = any value. the above are fine.

    Danilo A. said:
    2. How much delay does the Intermediate Deser-Ser introduce in the MIPI path?

    Max delay is ~ 2 lines of the transferred data. Please refer to this E2E thread.

    Danilo A. said:
    3. Can I use an MCU to configure the registers of Intermediate Deser-Ser chipsets, rather than depending on SoC1/SoC2?

    Yes, that is possible.

  • 0 in reply to Hamzeh Jaradat
    Prodigy 40 points

    Hi  

    Thanks for the suggestions.

    We have certain mandatory requirements also in terms of Serializer/Deserializer Chipsets.

    Our camera system currently includes UB913A, which accepts parallel input. I have a question regarding the possibility of introducing UB954A or UB936Q1 as the input for the Duplicator device.

    Our requirement is as follows:

    1. For SoC2, we want to connect UB913A as the Serializer.
    2. For SoC1, we have the flexibility to connect either UB913A, UB953A, or UB935Q1 as the Serializer.
    3. Additionally, near SoC2, we must use UB914A/UB960Q as Deserializer(this is a mandatory requirement)(parallel/MIPI).
    4. For SoC1, we can use UB954A, UB960Q, or UB936Q1, but it needs to provide MIPI-CSI2.

    Please advise on any potential design changes to accommodate these requirements, while ensuring the path to SoC2 remains unchanged.

    Looking forward to your suggestions.

    Regards

    Eric

  • 0 in reply to Eric Sonnabend
    TI__Guru** 116930 points

    Hi Eric,

    there is no problem with pairing the UB913A to the UB954 or UB936. Also, there is no problem with pairing the UB913A/UB953/UB935 with the UB954/UB960/UB936. Also pairing the UB913A with the UB914A/UB960 is fine. However, you cannot connect the UB954/Ub936 output (CSI-2) to the UB913A input (parallel)

  • 0 in reply to Hamzeh Jaradat
    Prodigy 40 points

    Hi  

    Are there any other Deserializer chipsets which can be used to duplicate the FPDLink3 input to parallel data(similar to UB954A duplicates MIPI)?

    Also, is there any mechanism/chipsets available from TI to convert the

    1. MIPI to Parallel data
    2. Parallel MIPI

    Regards

    Sebin Thankachan

  • 0 in reply to Eric Sonnabend
    TI__Guru** 116930 points

    Hi Eric,

    Eric Sonnabend said:
    Are there any other Deserializer chipsets which can be used to duplicate the FPDLink3 input to parallel data(similar to UB954A duplicates MIPI)?

    Do you mean, you are looking for a DES with dual outputs (parallel data)? If that is the question, the answer is no. we have only single output parallel data DES. However, you may use 12-Channel 1:2 MUX/DEMUX such as the TMUX162-Q1.

    Eric Sonnabend said:

    Also, is there any mechanism/chipsets available from TI to convert the

    1. MIPI to Parallel data
    2. Parallel MIPI

    we do not have a single-chip MIPI-parallel or parallel to MIPI. You may use a SER/DES solution to achieve that. i.e. parallel SER paired with a CSI DES, or vise-versa.

  • 0 in reply to Hamzeh Jaradat
    Prodigy 40 points

    Hi  

    Q1:

    Please find the attached diagram for reference.

    We hope this aligns with your earlier suggestion. To confirm, using a MIPI CSI-2 to parallel converter/bridge should address the issue, correct?

    Additionally, could you please advise on the required parallel data bit depth for the UB913? Should we plan for 10-bit, 12-bit, 14-bit, or 24-bit parallel data?

    Could you please specify the maximum achievable bandwidth in this pipeline, assuming a configuration without the MIPI-to-parallel bridge?

    Q2:

    You also mentioned an alternative approach using a serializer–deserializer (SerDes) pair. Is the attached diagram representative of the architecture you had in mind? If so, could you please confirm the maximum supported bandwidth for this configuration?

    Regards

    Sebin Thankachan

  • 0 in reply to Eric Sonnabend
    TI__Guru** 116930 points

    Hello Eric,

    Eric Sonnabend said:
    We hope this aligns with your earlier suggestion. To confirm, using a MIPI CSI-2 to parallel converter/bridge should address the issue, correct?

    Yes, this looks good to me.

    Eric Sonnabend said:
    Additionally, could you please advise on the required parallel data bit depth for the UB913? Should we plan for 10-bit, 12-bit, 14-bit, or 24-bit parallel data?

    The UB913A does support max 12-bit. This device has physically 12-data inputs only.

    Eric Sonnabend said:
    Could you please specify the maximum achievable bandwidth in this pipeline, assuming a configuration without the MIPI-to-parallel bridge?

    The bottle neck here will be the UB913A since it can support max 1.4 Gbps.

    Eric Sonnabend said:
    You also mentioned an alternative approach using a serializer–deserializer (SerDes) pair. Is the attached diagram representative of the architecture you had in mind? If so, could you please confirm the maximum supported bandwidth for this configuration?

    The UB935 path can support max 2.5 Gbps, and the UB914A path can support max 1.4Gbps