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Original question:

CDCE913-Q1: Jitter cleaner for differential clock

DS90UB928Q-Q1: DS90UB927&928 RxCLK jietter freq>f/4

han yunke
Prodigy 15 points

Part Number: DS90UB928Q-Q1
Other Parts Discussed in Thread: ALP

Hi TI team:

    In my project, I use the DS90UB927&928,for lvds singal transmission,To adress EMCissues,I add clock spreading to the LVDS clock output from the CPU to 927,with a spreading frequency of 31.5khz and a downward spread of 0.5%.but ,we observed screen flickering.if we disable the clock spreading effectively resolved the issue

    I noticed in the datasheet that the eye diagram test conditon  is: jitter frequency>f/40,I want to know about :

1/why we need such frequency;

2/cloud low-frequency power noise or thermal noise cause the CDR lose lock,just like the clock spreading cause  

Regards

Bruce

  • 0
    TI__Guru** 119220 points

    Hello,

    The team is out due to the Holidays. Responses will be delayed from Dec. 24 through Jan. 2.

    Thank you for your patience

  • 0 in reply to Hamzeh Jaradat
    TI__Expert 5193 points

    Hi Bruce,

    Can you confirm if you are using the EVMs for these devices?

    The DS90UB927 is not designed for SSCG on the oLDI input.

    The frequency specification lists the jitter margin is the acceptable amount of jitter the system can tolerate or the jitter on the output of the system.

    Low frequency power noise or thermal noise that is coupled into the system could affect CDR and FPD lock. We have design specifications for power and thermal relief that is designed to mitigate the effect from coupling onto the device's performance.

    Thanks,

    Ragav Subramanian

  • 0 in reply to Ragav Subramanian
    Prodigy 15 points

    Hi Ragav

    I am testing with my own designed circuit board

    if the 927 is not designed for SSCG,I will close the function in the CPU platform

    And i still have some questions regarding jitter frequency and hope to get your answers:

    1.In the 927 datasheet mentioned：the jitter frequency is specified in conjunction with 928 PLL bandwidth，i want to understand the connection between them,because in the specifications the jitter frequency is defined as a  range (fpclk/40<f<fpclk/20),while in my understanding,the PLL bandwidth is a boundary,a specific value.Dose tihs frequency range exhibit a peak in gitter gain,making it the most vulnerable part of the CDR?

    2.I have observed that when clock spreading(SSC) is active and the CDR loses lock, the LOCK pin is pulled down and then quickly pulled up again(several microseconds),but this status is not recorded in the 0x1c register. Is this behavior expected? 

  • 0 in reply to han yunke
    TI__Mastermind 37250 points

    Hi Han,

    I will review and get back to you tomorrow.

    - Fadi A.

  • 0 in reply to Fadi Abdulhameed
    Prodigy 15 points

    Hi Fadi

    Thank you  and we look forward to your response.

    Regards

    Bruce

  • 0 in reply to han yunke
    TI__Mastermind 37250 points

    Hi Bruce,

    Those older 92x parts don't support SSC or SSCG functions. For stable lock you need to turn off SSC from the source to reduce jitter on your CLK and avoid lock instability issues, etc. 

    For FPD-Link devices we recommend to qualify the following items related to signal transmission quality:

    - Channel s-parameters from the pins of the 927 to the pins of the 928 for comparison to the FPD-Link channel specifications document. 

    - PCLK input jitter to the input of 927:

    Attached Measurement Guide: 

    6866.92x-91x Jitter_measurment_Feb2023.pdf

    As a first step you can use MAP tool on ALP to verify that your link margin is ok between SerDes 

    Basically you need a SER and DES connected to each other then you can use the Des (928) ALP profile to run MAP tool to check your link margin. Here is an App note describing how this works. Ensure while the test is running you have local I2C connected to the Des (928) this link test can't be done from the Ser side.

    https://www.ti.com/lit/an/snla301/snla301.pdf?ts=1741787284105&ref_url=https%253A%252F%252Fwww.google.com%252F

    https://www.ti.com/lit/ug/snlu243/snlu243.pdf?ts=1741787282632&ref_url=https%253A%252F%252Fwww.google.com%252F

    han yunke said:
    In the 927 datasheet mentioned：the jitter frequency is specified in conjunction with 928 PLL bandwidth，i want to understand the connection between them,because in the specifications the jitter frequency is defined as a  range (fpclk/40<f<fpclk/20),while in my understanding,the PLL bandwidth is a boundary,a specific value.Dose tihs frequency range exhibit a peak in gitter gain,making it the most vulnerable part of the CDR?

    The 927/928 has a specific frequency range because there are frequencies that will be rejected by the FPD TX PLL and others that will be passed along onto the serialized stream. The range of f/40 - f/20 is what has been validated.

    han yunke said:
    2.I have observed that when clock spreading(SSC) is active and the CDR loses lock, the LOCK pin is pulled down and then quickly pulled up again(several microseconds),but this status is not recorded in the 0x1c register. Is this behavior expected? 

    Yes this behavior is expected. The LOCK pin reflects instantaneous CDR lock status and can toggle during very short transient events (µs-level) such as those introduced by SSC. The 0x1C register is filtered and requires the unlock condition to be present for longer duration to be recorded so brief LOCK drops may not be latched

    - Fadi A.