DP83TD510E-PODL-EVM: 2.4Vpp mode2

Hi Allan,

Sorry for the late reply due to the holiday season.

May I ask which register did you configure when you are setting Test mode 2? Here is the script we use for test mode 2:

• 000d 0001
  000e 08f8
  000d 4001
  000e 4000 //Set test mode 2 in MMD 01

  000d 001F
  000e 001F
  000d 401F
  000e 4000 //soft reset

Could you try to see if adding soft reset after the test mode 2 configuration help?

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Regards,

Hillman Lin

Hi Hillman,

Thank you for providing the script for Test Mode 2.

I noticed the syntax for the Soft Reset section at the end seems to use Indirect Register Access (via Reg 0x000D / 0x000E) targeting MMD Device 31 (0x1F).

000d 001F
000e 001F
000d 401F
000e 4000 //soft reset

Since 0x001F (PHY Control Register) is a standard base register, shouldn't we access it directly? Using the indirect method for a standard register seems unusual.

Could you confirm if the following direct write is sufficient and safer?

001f 4000 // Soft Reset (Direct Access)

Or is there a specific reason we must access it via MMD 31 for this specific PHY?

Thanks.

Suluclac Wang

Hi Wang,

You can also use direct register access for software reset. Both way work for to access the register 0x001F in MMD31 library.

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Regards,

Hillman Lin

Hi Hillman,

Thanks for confirming that the direct register access (0x001F) for Soft Reset works. We have verified our script configuration, and the settings are correct.

We have a critical request regarding the DP83TD510E-PODL-EVM performance:

We are using the Wurth 74930200 (350µH) transformer in our design, which matches the BOM of the TI EVM. However, we are seeing a marginal failure in the Test Mode 2 (2.4Vpp) Droop Test (we measured ~10.26% droop, which exceeds the 10% limit of IEEE 802.3cg).

Could you please confirm if the DP83TD510E-PODL-EVM actually passes the Test Mode 2 Droop Test (<10%) in your lab?

Since 350µH is physically marginal for the 2.4Vpp low-frequency requirement, we suspect the EVM might also be on the borderline or relies on the newer IEEE 802.3dd (25%) limit. Knowing the EVM's actual test result will help us decide whether we must change the transformer or simply update our test standard limits.

Thanks,

Suluclac Wang

Hi Wang,

Glad that script work on your side.

If possible, could you share the current test report that you have on DP83TD510E-PODL-EVM?

Are you powering up through cable or PoDL application while performing this test? We are planning to perform some PMA testing with current DP83TD510E-PODL-EVM

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Regards,

Hillman Lin

To clarify, the test results I mentioned (with ~10.26% droop) were measured on our custom hardware design, which is based on the DP83TD510E-PODL-EVM reference. We are not testing the physical TI EVM board itself.

Regarding the power setup: For this specific PMA testing, we are currently powering the DUT using an external DC power supply (direct power injection) to ensure stability, rather than powering it through the PoDL cable. We want to isolate the signal integrity performance first.

Regarding the test report you requested, I have already sent it to Allan. I will ask him to forward it to you shortly.

The reason we are requesting the DP83TD510E-PODL-EVM test report is that our design uses the exact same transformer (Wurth 74930200, 350µH) as the TI EVM. We suspect that with a 350µH transformer, it is physically challenging to meet the strict <10% droop limit (IEEE 802.3cg).

Could you please help confirm if the TI EVM itself is able to pass the 2.4Vpp Mode 2 Droop test with <10% result? This will help us determine if our marginal failure is expected behavior for this transformer specification.

Thanks.

Suluclac Wang

Hi Wang,

Understood, we will look into the compliance report on PoDL board and provide you an feedback later this week.

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Regards,

Hillman Lin

Hi Hillman,

Pleaes have a look the report and share your advice. 

2_4Vpp_004.pdf

Thanks.

Allan

Hi Allan,

Thank you for the report. we will review it.

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Regards,

Hillman Lin

Hi Allen,

Currently, our compliance scope is send out for calibration. We only have the some scope capture on the voltage droop. It seems like we are above 10% within 133.3ns when in the PoDL board when we power externally.

We will provide you an more detail update when we receive back the scope next week.

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Regards,

Hillman Lin

Hi Hillman, Allan,

Could you provide an update on the current status?

Thanks.

Suluclac Wang

Hi Wang,

Sorry for the delay. The scope calibration took longer than we expected. 

We did some initial study on the voltage droop performance. Could we start with changing some parameter on your side to see if that improve the PoDL performance?

• 
• Make sure the R117 and R126 are 39 ohms.
• Remove common mode termination R129 and R130
• Remove capacitors on the MDI lines to ground.

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Regards,

Hillman Lin