Part Number: SN65DP159
Background: We are designing a USB Type‑C test box to validate a DP Source without a real monitor and have a few follow‑up questions:
We know that SN65DP159 does not natively expose full DPCD. Does SN65DP159 expose any readable status bits over I2C that can serve as a coarse “link layer established” indicator?
* Per‑lane CDR/PLL lock
* Equalizer status
* Link detect / loss‑of‑signal
* Training state or achieved voltage swing/pre‑emphasis
* HPD and/or AUX activity indicators
If yes, could TI share the relevant register map (addresses and bit definitions) and any app notes or EVM guides on how to poll these?
If SN65DP159 is not suitable for this purpose, does TI have a DP sink or DP‑to‑HDMI bridge device that can act as a headless sink and expose link/DPCD, MSA (Main Stream Attributes), or video timing parameters via I2C for automated testing? Any recommended part numbers and EVMs would be appreciated.
For “headless DP Source production test” scenarios, what solution path does TI recommend, and is there a reference design? For example, a suggested combination of TI devices (retimer/sink, HPD/EDID emulation), application notes, or evaluation boards that enable:
* Simulated HPD and EDID to force mode selection
* Link training with status visibility
* Readout of link parameters and, ideally, output timing/frequency
Pointers to datasheets, register maps, app notes, and reference designs/EVMs would be very helpful.
