TDA4VL-Q1: SPI in/out test

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/**
 *  \file     McspiApp_Startup.c
 *
 *  \brief    This file contains the pinmux, interrupt and clock configuration.
 */
/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
#include "McspiApp_Startup.h"
#include "McspiApp.h"

/* ========================================================================== */
/*                         Structures and Enums                               */
/* ========================================================================== */

/* ========================================================================== */
/*                 Internal Function Declarations                             */
/* ========================================================================== */

/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */

/* ========================================================================== */
/*                          Function Definitions                              */
/* ========================================================================== */
/** \brief Start up sequence : Program the interrupt muxes / priorities */
void SpiApp_Startup(void)
{
    uint32 regVal;

    /* write Partition Lock Key 0 Register */
    CSL_REG32_WR(CSL_MCU_CTRL_MMR0_CFG0_BASE + CSL_MCU_CTRL_MMR_CFG0_LOCK1_KICK0,
        0x68EF3490U);
    /* write Partition Lock Key 1 Register */
    CSL_REG32_WR(CSL_MCU_CTRL_MMR0_CFG0_BASE + CSL_MCU_CTRL_MMR_CFG0_LOCK1_KICK1,
        0xD172BC5AU);
    /* Check for unlock */
    regVal = CSL_REG32_RD(CSL_MCU_CTRL_MMR0_CFG0_BASE + CSL_MCU_CTRL_MMR_CFG0_LOCK1_KICK0);
    while ((regVal & 0x1U) != 0x1U)
    {
        regVal = CSL_REG32_RD(CSL_MCU_CTRL_MMR0_CFG0_BASE + CSL_MCU_CTRL_MMR_CFG0_LOCK1_KICK0);
    }

    /* Unlock lock key registers for Partition 7: IO PAD
       configuration registers in MAIN_CTRL_MMR */
    /* write Partition 7 Lock Key 0 Register */
    CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_LOCK7_KICK0,
                0x68EF3490);
    /* write Partition 7 Lock Key 1 Register */
    CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_LOCK7_KICK1,
                0xD172BC5A);
    /* Check for unlock */
    regVal = CSL_REG32_RD(CSL_CTRL_MMR0_CFG0_BASE +
        CSL_MAIN_CTRL_MMR_CFG0_LOCK7_KICK0);
    while ((regVal & 0x1) != 0x1U)
    {
		regVal = CSL_REG32_RD(CSL_CTRL_MMR0_CFG0_BASE +
            CSL_MAIN_CTRL_MMR_CFG0_LOCK7_KICK0);
    }

    /* Enable MCU_MCSPI1 and MCSPI3 independently pin out */
    CSL_REG32_WR(CSL_MCU_CTRL_MMR0_CFG0_BASE +
        CSL_MCU_CTRL_MMR_CFG0_MCU_SPI1_CTRL,
            CSL_MCU_CTRL_MMR_CFG0_MCU_SPI1_CTRL_SPI1_LINKDIS_MASK);

    /* MCSPI 5 CS0 PAD configuration */
    regVal = CSL_REG32_RD(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PADCONFIG26);
    regVal = 0x40008U;
    CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PADCONFIG26, regVal);

    /* MCSPI 5 CS1 PAD configuration */
    regVal = CSL_REG32_RD(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PADCONFIG25);
    regVal = 0x40008U;
    CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PADCONFIG25, regVal);

    /* MCSPI 5 CS2 PAD configuration */
    regVal = CSL_REG32_RD(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PADCONFIG21);
    regVal = 0x40008U;
    CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PADCONFIG21, regVal);

    /* MCSPI 5 CS3 PAD configuration */
    regVal = CSL_REG32_RD(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PADCONFIG22);
    regVal = 0x40008U;
    CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PADCONFIG22, regVal);

    /* MCSPI 5 D1 PAD configuration */
    regVal = CSL_REG32_RD(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PADCONFIG34);
    regVal = 0x24000BU;
    CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PADCONFIG34, regVal);

    /* MCSPI 5 D0 PAD configuration */
    regVal = CSL_REG32_RD(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PADCONFIG28);
    regVal = 0x00008U;
    CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PADCONFIG28, regVal);

    /* MCSPI 5 CLK PAD configuration */
    regVal = CSL_REG32_RD(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PADCONFIG31);
    regVal = 0x40008U;
    CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PADCONFIG31, regVal);

    setI2C();
    /* Initialize profiling API's */
    AppUtils_ProfileInit (0U);

    /* Initialize memory sections  */
	AppUtils_SpiSectionInit();

    /* Interrup Registrations */
    SpiApp_InterruptConfig();

    return;
}

void setI2C(void)
{
    uint32 regVal = 0U;

    I2C_Params      i2cParams;
    I2C_Handle      handle = NULL;
    uint8           dataToSlave[4];

    /*
     * Configuring TCA6408A IO Exp  with addr 0x21
     * This io expander is controlled by i2c0
     * For Main MCAN4 P07 should be set to 0.
     */
     /* I2c PinMux */
    /* I2C0_SDL */
    regVal = 0x40000U;
    CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + 0x1C0E0U, regVal);
    /* I2C0_SDA */
    regVal = 0x40000U;
    CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + 0x1C0E4U, regVal);
    /* I2C initialization */
    I2C_init();
    I2C_Params_init(&i2cParams);
    i2cParams.transferMode = I2C_MODE_BLOCKING;
    i2cParams.bitRate = I2C_400kHz;
    i2cParams.transferCallbackFxn = NULL;

    handle = I2C_open(0U, &i2cParams);

    /* ------------------- step 1 Read & write Configuration register ------------------------------------*/
    /* Read the Config port 0 */
    dataToSlave[0] = TCA6408A_REG_CONFIG0;
    dataToSlave[1] = 0x0U;
    SetupI2CTransfer(handle, 0x21, &dataToSlave[0], 1, &dataToSlave[1], 1);
    
    /* writing 0 to p07 , 0 -> output mode, 1 -> Input mode*/
    dataToSlave[0] = TCA6408A_REG_CONFIG0;
    dataToSlave[1] &= ~(1 << 1);
    dataToSlave[1] &= ~(1 << 2);
    dataToSlave[1] &= ~(1 << 3);
    // dataToSlave[1] &= ~(1 << 7);
    SetupI2CTransfer(handle, 0x21, &dataToSlave[0], 2, NULL, 0);

    /* ------------------- step 2 Read & write output register ------------------------------------*/
    /* Read the Output port 0 */
    dataToSlave[0] = TCA6408A_REG_OUTPUT0;
    dataToSlave[1] = 0x0U;
    SetupI2CTransfer(handle, 0x21, &dataToSlave[0], 1, &dataToSlave[1], 1);
    
    /* writing 0 output p07 to 0 */
    dataToSlave[0] = TCA6408A_REG_OUTPUT0;
    // dataToSlave[1] &= ~(1 << 7);    /* STB  = 0 */
    dataToSlave[1] &= ~(1 << 3);
    dataToSlave[1] |= (1 << 1);     
    dataToSlave[1] |= (1 << 2);

    SetupI2CTransfer(handle, 0x21, &dataToSlave[0], 2, NULL, 0);

    return;
}

void SetupI2CTransfer(I2C_Handle handle,  uint32 slaveAddr,
                      uint8 *writeData, uint32 numWriteBytes,
                      uint8 *readData,  uint32 numReadBytes)
{
    bool status;
    I2C_Transaction i2cTransaction;

    I2C_transactionInit(&i2cTransaction);
    i2cTransaction.slaveAddress = slaveAddr;
    i2cTransaction.writeBuf = (uint8 *)&writeData[0];
    i2cTransaction.writeCount = numWriteBytes;
    i2cTransaction.readBuf = (uint8 *)&readData[0];
    i2cTransaction.readCount = numReadBytes;
    status = I2C_transfer(handle, &i2cTransaction);
    if(FALSE == status)
    {
        AppUtils_Printf(APP_UTILS_PRINT_MSG_NORMAL, "\n Data Transfer failed. \n");
    }
}

/** \brief Interrupt registrations*/
void SpiApp_InterruptConfig(void)
{
    OsalRegisterIntrParams_t    intrPrms;
    OsalInterruptRetCode_e      osalRetVal;
    uint32 idx;
    HwiP_Handle hwiHandle;
    const Spi_ConfigType *cfgPtr;

    /* Init */
#if (STD_ON == SPI_PRE_COMPILE_VARIANT)
    AppUtils_Printf(APP_UTILS_PRINT_MSG_NORMAL, APP_NAME
         ": Variant - Pre Compile being used !!!\n");
	cfgPtr = &SPI_INIT_CONFIG_PC;
    Spi_Init((const Spi_ConfigType *) NULL_PTR);
#else
    AppUtils_Printf(APP_UTILS_PRINT_MSG_NORMAL, APP_NAME
         ": Variant - Post Build being used !!!\n");
    cfgPtr = &SpiDriver;
    Spi_Init(cfgPtr);
#endif

    Intc_Init();    /* Interrupt handler initialized, here as other functions
                     * can use API's to clear pending interrupts if any
                     */

    /* We will have to use the routed interrupt number
        subsequently */
    /* Set the destination interrupt */
    for (idx = 0U; idx < cfgPtr->maxHwUnit; idx++)
    {
        if (cfgPtr->hwUnitCfg[idx].enabledmaMode == FALSE)
        {
            Osal_RegisterInterrupt_initParams(&intrPrms);
        #if (STD_ON == SPI_UNIT_MCSPI3_ACTIVE)
        #if (SPI_ISR_TYPE == SPI_ISR_CAT1 || SPI_ISR_TYPE == SPI_ISR_VOID)
            intrPrms.corepacConfig.arg          = (uintptr_t)Spi_IrqUnitMcspi3TxRx;
        #endif
        #endif
            intrPrms.corepacConfig.isrRoutine   = &SpiApp_SpiXIsr;
            intrPrms.corepacConfig.priority     = 1U;
            intrPrms.corepacConfig.corepacEventNum = 0U; /* NOT USED ? */
            intrPrms.corepacConfig.intVecNum        = APP_SPI_3_INT;

            osalRetVal = Osal_RegisterInterrupt(&intrPrms, &hwiHandle);
            if(OSAL_INT_SUCCESS != osalRetVal)
            {
                AppUtils_Printf(APP_UTILS_PRINT_MSG_NORMAL,
                                  ": Error %d !!!\n");
            }
        }
#if (STD_ON == SPI_DMA_ENABLE)
        else
        {
            /* DMA Tx Channel Interrupt */
            Osal_RegisterInterrupt_initParams(&intrPrms);
        #if (STD_ON == SPI_UNIT_MCSPI3_ACTIVE)
        #if (SPI_ISR_TYPE == SPI_ISR_CAT1 || SPI_ISR_TYPE == SPI_ISR_VOID)
            intrPrms.corepacConfig.arg          = (uintptr_t)Spi_IrqUnitMcspi3DmaTx;
        #endif
        #endif
            intrPrms.corepacConfig.isrRoutine   = &SpiApp_SpiXIsrTx;
            intrPrms.corepacConfig.priority     = 1U;
            intrPrms.corepacConfig.corepacEventNum = 0U; /* NOT USED ? */
            intrPrms.corepacConfig.intVecNum        = cfgPtr->hwUnitCfg[idx].dmaTxChIntrNum;

            osalRetVal = Osal_RegisterInterrupt(&intrPrms, &hwiHandle);
            if(OSAL_INT_SUCCESS != osalRetVal)
            {
                AppUtils_Printf(APP_UTILS_PRINT_MSG_NORMAL,
                                  ": Error %d !!!\n");
            }

            /* DMA Rx Channel Interrupt */
            Osal_RegisterInterrupt_initParams(&intrPrms);
        #if (STD_ON == SPI_UNIT_MCSPI3_ACTIVE)
        #if (SPI_ISR_TYPE == SPI_ISR_CAT1 || SPI_ISR_TYPE == SPI_ISR_VOID)
            intrPrms.corepacConfig.arg          = (uintptr_t)Spi_IrqUnitMcspi3DmaRx;
        #endif
        #endif
            intrPrms.corepacConfig.isrRoutine   = &SpiApp_SpiXIsrTx;
            intrPrms.corepacConfig.priority     = 1U;
            intrPrms.corepacConfig.corepacEventNum = 0U; /* NOT USED ? */
            intrPrms.corepacConfig.intVecNum        = cfgPtr->hwUnitCfg[idx].dmaRxChIntrNum;

            osalRetVal = Osal_RegisterInterrupt(&intrPrms, &hwiHandle);
            if(OSAL_INT_SUCCESS != osalRetVal)
            {
                AppUtils_Printf(APP_UTILS_PRINT_MSG_NORMAL,
                                  ": Error %d !!!\n");
            }


        }
#endif
    }
    return;
}

/** \brief None, SBL/GEL powers up the timers and clock sources */
void SpiApp_PowerAndClkSrc(void)
{
    /* Mcu module, when included will replace this operation */
    return;
}

#define SPI_START_SEC_ISR_CODE
#include "Spi_MemMap.h"

FUNC(void, SPI_CODE_FAST) SpiApp_SpiXIsr(uintptr_t SpiPtr)
{
    SpiApp_IsrType spiChIsr = (SpiApp_IsrType)SpiPtr;

    /* Associated Spi ISR */
    spiChIsr();
}

#if (STD_ON == SPI_DMA_ENABLE)
FUNC(void, SPI_CODE_FAST) SpiApp_SpiXIsrTx(uintptr_t SpiPtr)
{
    SpiApp_IsrType spiChIsr = (SpiApp_IsrType)SpiPtr;

    /* Associated Spi ISR */
    spiChIsr();
}

FUNC(void, SPI_CODE_FAST) SpiApp_SpiXIsrRx(uintptr_t SpiPtr)
{
    SpiApp_IsrType spiChIsr = (SpiApp_IsrType)SpiPtr;

    /* Associated Spi ISR */
    spiChIsr();
}
#endif

#define SPI_STOP_SEC_ISR_CODE
#include "Spi_MemMap.h"