Dear TI-Experts,
while we where performing the ETH-compliance test we faced two issues with our current design of the ETH-Interface.
1. We are failing the Template test in two points (F and H).
2. We also are failing the Master Filtered Jitter by around 200 ps
We have used the DP83867 in some of our designs already and had no issues with the compliance test before.
The schematics in this design are taken over from our known-good designs.
Troubleshooting:
We tried...
1. ...swapping DUTs, ETH-cables, compliance boards
2. ...changing values of center taps
3. ...following every step of the TI DP83867 Troubleshooting Guide (3.6 Compliance Debug)
www.ti.com/.../snla246c.pdf
- All measures to this point including adjusting register values did not show any effect on the issues.
4. After that we tried adjusting the Rbias from 11K to 10K. This resulted in passing the Template test completely (including points F and H).
However the Jitter Issue is still unaffected.
Our questions to you:
1. Do you have any ideas/experiences on what could be the cause of the observed issues?
2. Is adjusting Rbias an acceptable solution for the first issue? Is the performance of the PHY affected by this change?
3. Can you recommed any other measures to fix the jitter issue?