DS90UB947-Q1: A snowflake display abnormality was found in some DS90UB947 devices

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Hi Jianwei,

I have a few questions regarding the system and the failure mode:

1. Does this happen on all systems involved?
   • How many systems affected out of total systems? (Affected / Total)
   • Does this abnormality happen upon startup, or during runtime?
   • Does this happen every power cycle / initialization of the system?
2. If there are some systems that do not experience the abnormality, has there been an ABA swap for the IC?
   • What are the results for this?
     
     
3. The LVDS CLK is lowered, I would like some additional details about this.
   
   1. What is the original PCLK rate or video timings in which the screen is seen to flicker?
   2. What is the lowered PCLK rate or video timings that temporarily resolved the issue?
   3. What temperature is the device heated to?

These answers will guide the direction of the debug for this phenomenon, please let me know if you can provide the information as soon as possible and we can focus on the next steps.

Thanks!

Miguel

Hi Miguel

>>I have a few questions regarding the system and the failure mode:
>>
>>1 Does this happen on all systems involved?
Not all.

>>1.1 How many systems affected out of total systems? (Affected / Total)
300/10000

>>1.2 Does this abnormality happen upon startup, or during runtime?
Both.

>>1.3 Does this happen every power cycle / initialization of the system?
Yes.

>>2 If there are some systems that do not experience the abnormality, has there been an ABA swap for the IC?
Yes, ABA swap have been tried.

>>2.1 What are the results for this?
The snowflake display abnormal follow UB947.

>>3 The LVDS CLK is lowered, I would like some additional details about this.
>>3.1 What is the original PCLK rate or video timings in which the screen is seen to flicker?
The original PCLK rate 116985KHz.

>>3.2 What is the lowered PCLK rate or video timings that temporarily resolved the issue?
The lowered PCLK rate is 112511KHz.

>>3.3 What temperature is the device heated to?
85 centigrade

>>These answers will guide the direction of the debug for this phenomenon, please let me know if you can provide the information as soon as possible and we can focus on the next steps.

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Best

jianwei

Hi Jianwei,

Thank you for the organized information. At this point, I believe we should verify the errata implementation is correctly configured as given by the temperature sensitivities involved in the reproduction in this case.

Unfortunately, I cannot share the example initialization code in this public form as it is NDA confidential, but I will reach out to you via email with this example.

Can you please check or share the initialization code to ensure all the components of the errata are implemented?

My email will be m-bolante@ti.com.

Best,

Miguel

Hi Miguel

It not work at all.

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Best

Hi Jianwei, 

Thanks for checking and confirming.

I'm attaching further correspondence to the email to protect NDA initialization code, but here is a summarized list of those actions:

1. Let us characterize the RX specification for jitter across the different conditions
   • At normal unit and abnormal unit
   • At normal temperature and hot temperature
   • At normal PCLK and lowered PCLK
     
     
2. IC information (disclosed via email)

The purpose of these datapoints is to determine if there is some system-level marginality affecting the function of the devices.

Let us follow up offline.

Thanks!

Miguel

Hi Miguel

1. Since now guangzhou enter winter. The previous abnormal issue disappear without use lower PCKL. But heat it will reproduce. I think it the same case between “At normal temperature and hot temperature” and "At normal PCLK and lowered PCLK"

The jitter info will confirm later.

2. The IC is not need NDA. The IC is MTK 2712C chip. 

MTK2712 <==dual lvds===> UB947 <===dual fpdlink III====> UB948 <====> panel(1920*720@60FPS)

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Best

jianwei

Hi Jianwei,

Thanks for providing the additional details. Miguel will get back to you within 1-2 Business days.

Hi Jianwei,

I am reviewing the shared information now, thank you for providing. Please allow me one business day to get this aligned.

Best,

Miguel

Hi Jianwei,

I am still looking into this for you, thank you for your patience.

Best,

Miguel

Hi Miguel

got it.

Best,

jianwei

Hi Jianwei,

Thanks for you patience again - there is another test we can use to further isolate the device to either incoming OLDI clock or data lanes -

Can you try internal PATGEN with external clock? This will narrow down where to look for specification discrepancies. 

Please let me know if you need assistance setting this up.

Best,

Miguel