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TLIN1028-Q1: Datasheet value

Yusuke Okamoto
Intellectual 2290 points
Part Number: TLIN1028-Q1


Hi Team,

Could you support following customer questions?

Q1 Regarding tPWR, what are the values of MIN and TYP respectively?

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As far as my understanding, t_pwr depends on Vsup capacitance value. Is it correct?

Q2 When a reset is triggered by an abnormality (such as undervoltage), is the duration of the reset output maintained at Low also equal to tPWR?

Q3 What is the rise rate of the 5V output? Specifically, the time required for the voltage to rise from 0V to 5V.

Q4 Regarding to the unit indicated for RXD in datasheet, could you please confirm if there is a clerical error? (0.2*Vcc or 0.2*V?)
VOL(MAX)=0.2VCC, and if VCC=5V, then VOL(MAX)=0.2*5V=1V, is it correct? Where this 0.2*Vcc comes from?

Best Regards,

Yusuke

 

  • +1
    TI__Guru 59797 points

    Hi Yusuke,

    Q1. Yes

    Q2. No, nRST stays low until until UVCC rising threshold is met and ramps with VCC.

    Q3. Unfortunately, this is not specified and the 2 ms is the data sheets's closest timing reference to nRST high, since nRST release is tied to VCC ramp.

    Q4. No,RXD is an open-drain output referenced / pulled up to VCC and specified as 0.2 V max, per 2 to 10 kohms external pull-up, thanks.

    Best Regards,

    Michael.

  • 0 in reply to Michael Ikwuyum
    TI__Intellectual 2290 points

    Hi Michael,

    Q1  Could you provide one example of how to estimate tPWR from Vsup capacitance and Vsup power current source capability?

    Michael Ikwuyum said:
    Unfortunately, this is not specified and the 2 ms is the data sheets's closest timing reference to nRST high, since nRST release is tied to VCC ramp.

    Q2 Could you teach me slew rate in this case? Customer need to meet rise time requirement of MCU, which is 0.05V/ms between 0V to 5V. 

     

    Q3 Regarding the reset output, could you please confirm whether there is a hysteresis voltage for the VCC voltage monitoring? If yes, what is the value of the hysteresis voltage?

    Q4 Regarding UVcc5r and UVcc5f, Is my understanding correct?

  • 0 in reply to Yusuke Okamoto
    TI__Guru 59797 points

    Hi Yusuke,,

    Q1. The most accurate method should be to measure VCC and nRST on the real board with the real MCU load.

    VSUP cap mainly plays a role if too slow I.e, if significant enough for VSUP to ramp too slow as VCC regulation relies on VSUP meeting its threshold but this is typically not the case with the recommended 100 nF for VSUP. Hence, it's ramp in us should be negligible to matter in tPWR in ms

    However, basic cap ramp dV / dt can be used ≈ (I_SBC - I_LOAD) / C_VSUP where t = (C_VSUP * change in V) / (I_SBC - I_LOAD)

    For example C_VSUP  of 100 nF, target change in V as 4.2 V U_VSUPR, 10 mA current available for charging after subtracting other loads;

    • where t_VSUP = (10 uF * 4.2) / 10 mA as 42 us

    Q2. dV / dt implies 0.05 V / ms as t = 5 V / 0.05V/ms as 100 ms. Would recommend to reference the tPWR of 2 ms and scope VCC ramp with their load then compute V / t as the slew rate.

    Q3. Yes, 4.7 - 4.45 = 0.25 V (typ) for example. However, note deglitch time tDET (UVCC). Hence, short dips should not trigger.

    Q4. Yes, thanks.

    Best Regards,

    Michael.