LMH0318: LMH0324 and LMH0318 - Signal Integrity Issues

Hi Andrew, 

Could you describe the problem in more detail? What is the test procedure and setup and what is the error you are seeing? Is the BER increasing?

I do not see a glaring issue on the schematic and the layout. Have you tried removing D10 on LMH0324 and see if the issue persists? I am wondering perhaps the ESD diode is causing impedance mismatch, or activates causing signal degradation. 

Best,
J

Hi J,

I'm testing with a Phabrix SDI signal generator and analyser. I'm doing a loop back test where the I generate the signal on the input and read it back on the output. I was finding that I was getting random lines and small artefacts on my display and the during the bit error check I was getting frequency error, see below. Although when I left it to run over night it did eventually settle down and no more errors occurred. I have also tested this board within the system and the screen flickered for the first 5-10 minutes before eventually settling and running as expected.

I have not tested without the ESD diodes yet. On a previous version of this PCB we were finding the LMH0325 and LMH0318 were getting damaged and it was suspected to be due to ESD.

I have also included a measured eye diagram below.

Thanks,

Andrew

Hi Andrew, 

Thank you for the information. 

We also have Phabrix SDI generator so let me try to recreate this using our EVMs. 
I have set up Phabrix with our EVMs and I am currently sending PRBS-31 patterns. It has run some time, but I do not see any errors. What pattern have you sent out of the generator? I am curious so that I can most closely replicate this issue. 

I also wonder if this can be CDR lock issue. Can you try to re-lock on the CDR once the issue happens and see if the issue completely disappears?

Best,
J

Hi J, Phabrix settings in image below.

For the CDR re-lock, can this be done manually? We have not set up the devices to be controlled though software. I have a green LED on the LOCK pin which is switch on, suggesting that CDR is locked.

Thanks,

Andrew

Hi Andrew, 

You need register access to CDR re-lock. Also, there may be a chance CDR has to be disabled because the signal is slow. 
Would it be possible for you to get I2C or SPI access to the IC?

I tried with our Omnitek SDI generator which supports SD resolution and I see that CRC error is going up even when we loop back the output signal directly into the input. Would it be possible that Phabrix generator is incorrectly flagging CRC errors? Have you tried directly looping back the output signal into the input?

Best,
J

Hi J,

Unfortunately not, we dont have access to SPI or I2C so I wont be unable to reset the CDR. I will try however, running at 3G SDI and see if that prevents the CDR from failing to lock from being slow. The CDR pin is going high though, which suggests that it is locking correctly.

One thing I don't understand is why it would consistently fail to lock on one channel but not others? Why doesn't power cycling seem to resolve it.

Thanks,

Andrew

Hi Andrew,

So, it only happens consistently on one channel? If so, could you do a ABA swap to see if the issue follows the chip or the layout? Since the four channels have the same layout, I wonder if you could switch the chip between the channels and see if the issue stays with the layout or the chip.

Best,

J