DS92LV16: power up issues

Hi Chris, 

Can you describe the behavior of the device that is improper? How were you trying to use the device after you applied power, and how long had Vcc been above 2.2V once you tried to use the device? 

Regards,

Matt

Hi Matt Thanks for responding

in answer to your question, the devices parallel side is attached to and FPGA which doesnt get configured and start driving the device till several seconds after power up. 3.3vpower up behaviour is normal.

By improper behavior i mean it does not achieve lock with another device at the end of the serial link. We have a 'tried and tested' protocol driving the SYNC till the LOCK is achieved at the receiver. We have used this device for over ten years in multiple designs. this is the first time i have seen this issue.

The device seems to get itself in this 'locked up state' at power up no amount of FPGA reconfiguration cures it. The device deosnt have an external reset line but i found by experimentation that by holding the TCLK,DIN,REFCLK lines to the device static, this forces a kind of reset. Thereafter the device  locks up as normal with another device without any issues. FYI The DEN,REN are pull up permanently active and the PWRDN pins are pulled innactive.

My investigations are on going, I just posted to the forum to see if anyone else had seen similar behaviour, or maybe an original designer may have an idea

I am confident about the general PCB layout and decoupling etc as this is a much used device for us.

Hi Chris, 

Are you just seeing this behavior with one unit, or are you seeing it with multiple units when you try to replace it? 

Regards,

Matt 

Hi, sorry for delay in replying,

we are seeing this on multiple units. We have a working fix to keep signals to the device static for a couple of seconds.

Regards

Chris

Hi Chris,

So to make sure I'm understanding youre use case correctly, you are driving the SYNC pin high on the downstream serializer to generate the sync-pattern that consists of 8-bits of data high followed by 8-bits of data low for the deserializer in question to lock to. Is that correct? 

If so, does the /LOCK pin ever go low temporarily, or does it always stay high? Are you able to confirm that the downstream serializer is outputting the expected sync-pattern? 

Also, can you try the following power up sequence if you aren't already: Power up all VDD pins together, apply clocks (RefCLK & TCLK), and then bring /PWDN powerdown pins high to enable the transmit and/or receive channels. 

If you could share a schematic of how these devices are connected, that would be helpful. 

Regards,

Matt

Hi Matt

yes sync pin is driven as you say, correct.

lock pin does seem to go low sometimes yes, but usual failure mode is sync pin high at both ends lock signals at receiving ends never goes low... 

I can't guarantee the serial pattern being sent when SYNC is high, nor can i guarantee data passes through our serial link to the receiving chip un corrupted. However. the serial link integrity is normally good and i have not detected any failures once the links are up and locked.I will try and check this with scope if i can.

The power up sequence you request is also going to be tricky as PWDN signal are not actively driven, they are just pulled up. I will work on this too

Schematic attached.. we have 12 of these on one board (0,1,2,3,4,5,6,7,8,910,11).
My test mode link uses SFP serial cables to link serial tx 0 to serial rx1 and viceversa, 2to3, 4to5 etc..

just to confirm we do now have a workaround for this now. We hold all signals we can actively drive (DIN, TCLK and SYNC.), in a static state following power up for a few seconds then the chip behaviour returns to normal.

thanks again

Chris