Other Parts Discussed in Thread: LSF0002,
Hi Support Team,
I would like to request your assistance in reviewing the PCA9306DCUR circuit design.
In our current setup, the power-up sequence of "P3V3_STBY" occurs significantly earlier than "P1V8". This timing gap causes leakage current to flow to the A-side when "EN" and "VREF2" are already powered. To mitigate this, I have implemented an additional circuit to ensure that power is supplied to "EN" and "VREF2" only after the "P1V8_PWRGD" signal becomes ready.
Could you please confirm if this approach is appropriate? If you have any better alternatives or recommendations, please let us know. Thank you for your support.
