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DS90CR218A Channel link deserializer question

Jelko Huysmans
Prodigy 30 points
Other Parts Discussed in Thread: DS90CR218A, DS90CR217

Hello,

I am using a DS90CR218A / DS90CR217 serdes pair. For a new design I will be using an FPGA to do the serializing. Is the serializer just simply converting 7:1 or is there a synchronizing sequence used or are there extra parity bits sent or anything like that?

Regards

  • 0
    TI__Expert 5175 points

    Greetings -

    The bit mapping as shown in the datasheet provides the bit locations and channel number.  The Channel Link (gen 1)  Ser/Des do not encode or add extra bits.  Each channel carries 7 bits, and the clock line is actually composed of 4 bits one state and three the other (not 50% duty cycle).  The placement of the LVDS rising edge is critical for the data recovery in the DES.  The discrete SER parts tend to have strong jitter rejection and filtering and precise LVDS bit and edge placement.  If you build a integrated SER, it too will need to have these attributes for successful data recovery in the DES. 

    John Goldie
    DPS APPS / SVA