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DP83TC812S-Q1: Register Settings

Priyanka Nanda
Prodigy 20 points
Part Number: DP83TC812S-Q1


Hi,

Can I know what register settings will be needed to enable this set of configuration?

  1. Full Duplex + 100Mbps
  2. Master Mode
  3. Disable auto-MDIX and set Static MDI
  4. Disable all TC10,  sleep and wake up function and IEEE-power down settings
  5. Set both LEDs to TX Activity
  6. Disable auto-polarity. Set Forced Normal Polarity
  7. Enable MAC Interfaces Mode as SGMII or RGMII
  8. Disable all power save mode settings
  9. Set the media operating mode as Cu SFP
  10. Disable all interrupt mask
  • 0
    TI__Prodigy 225 points

    Hi Priyanka,

    Please see my response below:

    1. No configuration is needed. This device only supports Open Alliance and IEEE 802.3bw 100BASE-T1 specification.

    2. Strap pin-35 with 2.9kΩ resistor for master mode.

    3. This phy only supports 100Base-T1. No audo-MDIX functionality exists.

    4.

    - VSLEEP pin should be connected to VDDA (or any 3.3 V supply source).

    - WAKE pin should be pulled up to corresponding VSLEEP supply connection directly or through a resistor lower than 10 kΩ. WAKE pin can't be pulled up to VDDIO/VDDMAC supply.

    - INH can be left floating.

    - Write reg<0x018B>[8] = 1 

    5. LED configuration is set through register 0x0450 and 0x0451
    For LED_0 (pin 35) blink on TX activity, write register:
    reg<0x0450>[3:0] = 0x2

    For LED_1 (pin 6) blink on TX activity, write register:
    reg<0x0450>[7:4] = 0x2

    6. Disabling of auto-polarity correction is achieved via register 0x0553. 

    We generally do not recommend doing this as we've seen some linkup issues in previous customer cases. May I ask why you are inquiring about disabling auto-polarity detection?

    7. MAC interface mode can be strapped using pin 24, 25, 26. Please see datasheet table 7-20 (Bootstraps) and 7-24 (MAC Interface Selection Bootstraps) for more detailed strapping options.

    8. By default, power save mode is turned off.

    9. This device does not support copper SFP. This device is designed for single unshielded twisted pair cables.

    10. To disable interrupts write register:
    reg<0x0011>[1] = 0

    Could you share more about your use case? Your questions about disabling auto-MDIX and copper SFP support suggest this automotive 100Base-T1 PHY may not be the best fit. I'd be happy to help recommend a PHY that may better fit your needs.

    Best Regards,

    Charles

  • 0 in reply to Charles Wang
    Prodigy 20 points

    Thanks Charles for the detailed response. We do need an automotive part for our application, just the requirement of the environment is different.

    I had a few more questions:

    1. Which register controls the power save mode?

    2. What register settings are needed to enable RMII and SGMII mode?

    3. Can we disable auto-neg on the SGMII and RMII interface?

    4. Can I know what type of link-up issues you have seen earlier with auto-polarity disabled?

    5. How do you set the SQI threshold value?

    6. How is the TDR function enabled? What register read/write is required to perform TDR?

    If possible, can we catch up on a call to discuss our use case and the related configuration?

  • 0 in reply to Priyanka Nanda
    TI__Prodigy 225 points

    Hi Priyanka,

    Please see my responses below: 

    1. Can you explain what you mean by power-saving mode? This PHY supports TC10 sleep, IEEE power down, and standby mode.
    2. Register access is not need to configure Mac modes on startup. Strapping the device according to the bootstraps listed in table 7-24 (MAC Interface Selection Bootstraps) is enough to configure the PHY into RMII and SGMII mode.
    3. To disable auto-negotiation: 
      1. RMII does not support auto-negotiation 
      2. To disable SGMII auto-negotiation: Write reg<0x608>[0] = 0x0
    4. I wanted to point out that disabling auto-polarity on the master side is inconsequential since the slave device is the one correcting to the master's polarity. We don't recommend disabling this feature. May I ask again the purpose of this question? 
    5. SQI thresholds are preset according to the levels required by Open Alliance specifications.
    6. Please see SNLA389 which describes TDR test configuration for DP83TC812.

    We don't support calls over e2e queries. Sorry for the inconvenience. Please reach out to your FAE for additional support. 

    Best,

    Charles Wang

  • 0 in reply to Charles Wang
    Prodigy 20 points

    1. I mean all the modes that affect the power in any way - like TC10, IEEE or standby mode. Can we read the configuration of the register values linked to these modes in order to ensure that the bits doesn't get flipped in any EMI/radiation type of environment? 

    4. We are working in a highly deterministic type of network where we need to fix the polarity of the PHYs, and the cable on both end. 

    Thanks for your response and providing all the required details.

  • +1 in reply to Priyanka Nanda
    TI__Prodigy 225 points

    Hi Priyanka,

    Sorry for the delay. Thank you for providing me more details. Your use case is more clear to me now.

    1. Configuration registers for these modes:
      1. TC10:
        1. Follow snla411, section 8, Configuration for non-TC10 Applications. This is the same as my previous response
        2. You can monitor TC10 disabled by checking: reg<0x018B>[8] = 0x1
          1. (snla411)
      2. IEEE power-down mode:
        1. Normal mode: reg<0x0>[11] = 0x0
        2. IEEE power down mode: reg<0x0>[11] = 0x1
      3.  Standby mode:
        1. Normal mode: reg<0x1F>[7] = 0x0
        2. Standby mode: reg<0x1F>[7] = 0x1

          4. Understood. Please follow these two register writes to force polarity of MDI. Register 0x533 table. 

    1. Enable force polarity: reg<0x553>[13] = 0x1
    2. Set polarity force value:
      1. Normal polarity: reg<0x553>[12] = 0x0
      2. Inverted polarity: reg<0x553>[12] = 0x1

    Best,

    Charles Wang