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SN65DSI86: SN65DSI86 No Output

Neil Race
Prodigy 10 points

Part Number: SN65DSI86
Other Parts Discussed in Thread: TEST2

We are using the TI SN65DSI86 in our product for the first time. I’m struggling to get any video output from the bridge IC. I'm just trying to prove the DisplayPort works at the moment so I'm trying to just output colour bars, which can be enabled in register 0x3C by writing a 1 to bit 4.

 

It can successfully read the EDID and link train with the monitor but I get no video output at all. I’ve tried to enable the SMPTE colour bars to output but still nothing on the monitor. We are using Linux V6.12. To enable colour bars, the driver is loaded and it successfully link trains. After that I write:

 

i2cset -f -y 16 0x2c 0x3c 0x10

 

to enable the colour bars. It’s connected to a 1920x1080 monitor and has successfully link trained, see register 0xF1, bit 0 below.

 

This is a snapshot of the register map where I have enabled the colour bars output on Display Port.

 

     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef

00: 36 38 49 53 44 20 20 20 02 00 86 00 00 01 00 00    68ISD   ?.?..?..

10: 26 00 58 00 00 00 00 00 00 00 00 00 00 00 00 00    &.X.............

20: 80 07 00 00 38 04 00 00 00 00 00 00 2c 00 00 00    ??..8?......,...

30: 05 00 00 00 94 00 24 00 58 00 04 00 10 00 00 00    ?...?.$.X.?.?...

40: 55 75 00 00 80 00 98 08 65 04 c0 00 29 00 2c 00    Uu..?.??e??.).,.

50: 05 00 80 07 38 04 20 00 40 d2 0c 00 11 00 30 00    ?.??8? .@??.?.0.

60: a0 60 a4 00 20 01 01 01 00 00 00 00 00 00 00 00    ?`?. ???........

70: 00 00 00 00 00 01 02 01 80 81 77 00 00 00 00 00    .....?????w.....

80: 00 00 00 00 00 00 00 00 5e 1f 7c f0 c1 07 1f 7c    ........^?|????|

90: f0 c1 07 34 21 10 01 04 01 00 00 00 00 00 00 00    ???4!????.......

a0: 01 ff ff 00 00 00 00 00 00 00 00 00 00 00 00 00    ?...............

b0: 04 78 ac ac 08 6c 9c 9c 0c 5c 5c 5c 0c 0c 0c 0c    ?x???l???\\\????

c0: 3f 3f 0f 00 00 00 00 00 00 00 00 00 00 00 00 00    ???.............

d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................

e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................

f0: 03 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00    ?...............

 

Any help would be greatly appreciated.

  • 0
    TI__Mastermind 28750 points

    HI Neil,

    Thank you for sharing the findings and register read for this. 

    Are you testing this on the EVM or your custom board? On the custom board, what is the REFCLK frequency and is there valid clock input?

    Best regards,
    Ikram

  • 0 in reply to Ikram Haque
    Prodigy 10 points

    Hi Ikram,

    We are using a custom board. The reference clock is 27 MHz and the clock looks good and stable.

    Neil

  • 0 in reply to Neil Race
    TI__Guru** 115540 points

    Hello,

    Thank you for your message. Our team is currently out of office due to the public holiday. We will respond to your request when we return on 01/20/2026. Thank you for your understanding.

  • 0 in reply to Hamzeh Jaradat
    TI__Mastermind 28750 points

    Hi Neil,

    Are the programmed timings exactly the same as the display specifications? These values can be found on the display datasheet including the blanking timings.

    Or is the host reading the EDID to get these values?


    To enable the color bars, how did you generate the script and is it following the sequence (including delays, and resets) as shown in the datasheet? Could you share the current script for initialization?

    Best regards,
    Ikram

  • 0 in reply to Ikram Haque
    Prodigy 10 points

    Hi Ikram,

    It is reading the EDID and using the display timings from the monitor.

    We are using the driver supplied in Linux V6.12, https://github.com/nxp-imx/linux-imx/blob/lf-6.12.y/drivers/gpu/drm/bridge/ti-sn65dsi86.c. I believe this driver is following the recommendations from the specification. To enable colour bars, the driver is loaded and the following command is used:

    i2cset -f -y 16 0x2c 0x3c 0x10

    This writes 0x10 to register 0x3C, which should enable color bars.

    Regards,

    Neil

  • 0 in reply to Neil Race
    TI__Mastermind 28750 points

    HI Neil,

    Please give me 1-2 days to look further into this issue and get back to you.

    Best regards,
    Ikram

  • 0 in reply to Ikram Haque
    TI__Mastermind 28750 points

    Hi Neil,

    The semi-auto link training passes and the test pattern registers are programmed. The DP data rate and lane count are also sufficient for this resolution. 

    The 0x5A register is set to 0xD2, this has ASSR enabled. Could you check whether this panel supports ASSR? Is this panel for DP or eDP applications? 
    DP panels do not support ASSR, and eDP panels may or may not support it.

    In the schematic, is TEST2 pin set high or low?

    If possible, you could also share the panel datasheet and details here for the timings/EDID and eDP/DP settings.

    Best regards,
    Ikram

  • 0 in reply to Ikram Haque
    Prodigy 10 points

    Hi Ikram,

    Register 5A is 0x0C. I forgot to mention that I modified the driver slightly to turn ASSR to "Standard DP Scrambler Seed".

    It's connected to a standard DisplayPort monitor, not eDP so I don't have the datasheet for it unfortunately. The application for this is to connect to standard DisplayPort monitors and/or using active DP to HDMI adapters to connect to a HDMI monitor.

    The TEST2 pin is pulled high to 1.8V with a 10k resistor.

    Regards,

    Neil

  • 0 in reply to Neil Race
    TI__Mastermind 28750 points

    Hi Neil,

    This previous E2E mentions using with DP with no ASSR: RE: SN65DSI86: Using the Bridge as DSI to DisplayPort (not eDP)

    Copied:

    DSI86 is designed with ASSR enabled by default to support the eDP panel. Most DP monitors or panels do not support ASSR. To support DP monitors, DSI86’s ASSR will need to be disabled by making ASSR_CONTROL read/write instead of read-only. The first step to make ASSR_CONTROL read/write is to make sure TEST2 pin is be sampled high at the rising edge of EN pin. It is recommended to pull TEST2 pin to 1.8V thru a 1k to 10k resistor. Once TEST2 is high, the following steps must be performed:

    1. Write 0x07 to register 0xFF. This will select Page 7.
    2. Write 0x01 to register 0x16. This will make ASSR_CONTROL to be read/write.
    3. Write 0x00 to register 0xFF. This will select Page 0.
    4. Write 0 to bits 1:0 at register 0x5A. This will change from ASSR to Standard DP.

    Please follow these steps to disable ASSR. We can discuss further on the meeting.

    Best regards,
    Ikram

  • 0 in reply to Ikram Haque
    Prodigy 10 points

    Hi Ikram,

    ASSR is already 'disabled', as I previously mentioned I modified the driver to set ASSR to "Standard DP Scrambler Seed" and register 0x5A is 0x0C. The modifications do exactly as above before it reads the EDID and before it starts link training.

    Regards,

    Neil

  • 0 in reply to Neil Race
    TI__Mastermind 28750 points

    Hi Neil,

    On the TCON or display receiver is there any function to read the DP incoming MSAs (main stream attributes) to check whether the incoming video data is as expected? Since link training is confirmed, can it be confirmed that there is activity on the DP outputs?

    Is this display's DP interface verified working with any other sources such as a PC? We would just want to confirm that there is not a different issue here such as backlight or display not being enabled.

    Initially, how is the device reading the EDID? Is this process also integrated into the driver?

    Best regards,
    Ikram

  • 0 in reply to Ikram Haque
    TI__Mastermind 28750 points

    1/30 Update:

    The DP lane assignments for each pin were swapped to match the DP connector. After changing the lane assignments as needed, using the 0x59 register, color bars output was successsful.