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DP83867IR: Ethernet forced master error

Rishav Verma
Prodigy 40 points

Part Number: DP83867IR
Other Parts Discussed in Thread: AM625

Hi, 

I am using DP83867 with TI Am625 processor, and getting the error as below, where the phy is getting detected but the link is not up, due to forced master error, but it is configured as auto in the dts as well as in hardware, 

Please review the schematic for potential error and the possible resolution for the same. 

 

Settings for eth0:
        Supported ports: [ TP    MII ]
        Supported link modes:   10baseT/Half 10baseT/Full
                                100baseT/Half 100baseT/Full
                                1000baseT/Full
                                1000baseX/Full
        Supported pause frame use: Symmetric
        Supports auto-negotiation: Yes
        Supported FEC modes: Not reported
        Advertised link modes:  10baseT/Half 10baseT/Full
                                100baseT/Half 100baseT/Full
                                1000baseT/Full
                                1000baseX/Full
        Advertised pause frame use: Symmetric
        Advertised auto-negotiation: Yes
        Advertised FEC modes: Not reported
        Speed: 1000Mb/s
        Duplex: Full
        Auto-negotiation: on
        master-slave cfg: forced master
        master-slave status: resolution error
        Port: Twiwted Pair
        PHYAD: 1
        Transceiver: external
        MDI-X: Unknown
        Supports Wake-on: ubgs
        Wake-on: ubgs
        SecureOn password: ff:ff:ff:ff:ff:ff
        Current message level: 0x000020f7 (8439)
                               drv probe link ifdown ifup rx_err tx_err hw
        Link detected: no

 

ethernet section.jpg

Thanks, 

Rishav 

  • 0
    TI__Mastermind 26771 points

    Hi Rishav,

    Can you access the PHY registers via MDIO?

    Why are there capacitors on the MDI line? We typically do not see such design and that can cause link failure.

    Best,

    J

  • 0 in reply to J
    Prodigy 40 points

    Hi J, 

    Thanks for your response, 

    Yes we can read the MDIO registors (we can read and write all the phy registors succesfully)

    Key observations: 

    Loopback test failed

    phytool read eth0/0/0x10
    0x5048

    phytool read eth0/0/0x0e
    0x0017  # After running TDR test
    hytool read eth0/0/5
    0x0000  # Link partner ability register is EMPTY

    Please respond with your inputs on the same. 

    Thanks, 

    Rishav 

  • 0 in reply to Rishav Verma
    TI__Mastermind 26771 points

    Hi Rishav, 

    Which loopback have you tried?
    Can you remove the capacitors (C66 to C73) and see if the PHY links up?
    Can you also measure first link pulse on pair A and B of the MDI line?

    Best,
    J