TMDS1204: TMDS1204RNQR IC

Hi,

The same pin strapping for HDMI 2.0 should work for 2.1. 
To capture eye diagram, we typically use Keysight compliance SW.

Best,

J

Hi,
Attached is my HDMI 2.1 Architecture, how the setup should be. 
In this setup, anything we are missing, for FRL Mode. Please suggest your idea.

Hi, 
You don't seem to miss anything. It should work. What is the issue?

Best,
J

Hi,
We have test setup like, one carrier board as Tx, FRL data is sending from the TX board to the Rx Carrier board.
While passing FRL data from the TX board, the Data is receiving to the RX board after that we are observing, Clock error in the terminal., which is Link clock Error, video clock Error, Skew Lock Error.
If you are facing any issues, like this before. Why those clock Error is coming. 
Attached Error print snap for your reference.

Hi, 

1. If you have I2C access, can you check register 31h and ensure that it is a non-zero value?
2. Can you probe TMDS clock lane and see if there are no clock signal when FRL is being transmitted? I see that the log says TMDS reference clock is being changed when FRL is being streamed, but there should be no clock change for TMDS since FRL does not send clock signal. 
3. Are you using fan out buffer for the clock lane? If so, is it enabled?

Best,
J

Hii,
1. We are not checking i2C register address, because the TMDS1204 IC is in Pin strapping mode now.
2. Checked clock behaviour on HDMI connector pin itself, both Tx and Rx board, there is no frequency observed, while data is transmitted from the Tx board to Rx board. And, we confirmed, that the board is in FRL board, so 4 pairs of Data line is transmitted and no clock observed in that.
3. Yes, we are enabled Fan out buffer also., based on our Mode pin strapping,

Hi Vaishnavi, 

Can you share the schematic? In this case, is DDC snooping enabled and connected to LV_SDA and LV_SCL pins? If snooping is disabled, TMDS1204 defaults to HDMI 1.4 so that may be the reason why it is not transitioning into HDMI 2.1. 

Best,
J

Hii,
Attached HDMI IN and OUT schematics section for your reference.
Now, we are facing CDR Clock lock issue, is there anything to see in Hardware section. please recommend.

Hi, 

Is the CDR lock issue for FRL or TMDS?
If this is the same board that worked for TMDS, but not FRL, this is most likely the issue on the endpoint's receiver not being able to recover the signal, not the HW connection of the device issue. 
Have you tried increasing the EQ?

Best,
J

Hi,
The CDR issue observed on FRL mode.
And the same board setup is working for TMDS and not working for FRL mode.
Can you please explain how to increase the EQ, is there an pin strap setting? is there.

Hi, 

You can change the EQ via EQ0/EQ1 strap setting:

Below is the table for strap setting:


Best,
J

You mentioned like try to increase the EQ value which means, in above settings EQ Settings - 15 is OK for Rx and Tx board. EQ1 - 1 (for Rx and Tx) and EQ - 0 (for Rx and Tx).
Is this configuration is Correct or please suggest the exact pin strap settings for EQ0 and EQ1 for Tx and Rx board.

Hi, 

EQ setting will depend on your board design. I would suggest to increase by one or two from the current EQ setting. What is the current EQ setting?

Best,
J

Hi J,
Now the settings will be EQ0 - F and EQ1 - R in TX board.
Please suggest, in which setup EQ value has to be increase, RX board or TX board.

And you suggest one or two value has to be increased from the current EQ setting.
Tried EQ0 - 0 and EQ1 - F in Tx board as per the data sheet EQ settings. Still we are facing Clock error and CDR lock issue.
Regards,
Vaishnavi

Hi Vaishnavi, 

Did the number of errors decrease?
Does CDR lock error only happen with this particular connection?
What is the HDMI cable length? Have you used short cable and see the error occur? I want to see if this is electrical issue or if the source is not sending out the good data. If it is not an electrical issue, you will have to contact the video source vendor. 
Have you also tried probing the HDMI signals and capture eye diagram?

Best,
J