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TXE8124-Q1: TXE8124 Input Latch

Bin Hu
Prodigy 140 points

Part Number: TXE8124-Q1
Other Parts Discussed in Thread: TXE8124

hi, Expert 

If TXE8124 Input Latch function is Disable , the Inport Port Register content is the same as the port value ;

But , If Input Latch function is Enable,  the Inport Port Register content is always the previous value .

For example, when Power on , the P0.0 is Low level , we read it as 0 , even the P0.0 is HIGH level , we read it still 0 . Maybe the IC is latched . 

I want to check :

  1.  How to deal with this issue when Latch function is Enable?

  • 0
    TI__Mastermind 37820 points

    Hello Bin,

    We are looking into this and will respond shortly.

    Regards,

    Josh

  • 0
    TI__Mastermind 37820 points

    Hello Bin,

    Thank you for your message. Let me add to the description of this register:

    The bus holder register enables or disables the input latch function of the GPIO pins. The feature is available only when the pin is configured as an input pin.

    When the register bit is cleared, the corresponding input pin state is not latched. A state change in the corresponding input pin generates an interrupt. The interrupt is cleared when the corresponding input port register is read. If the input goes back to its initial logic state before the read is completed, then the interrupt is cleared.

    When the input latch bit is set, the corresponding input pin state is latched. A change of state on the input pin generates an interrupt and a read of the input port register clears the same. However, if the input pin returns to its initial logic state before the input port register is read, then the interrupt is not cleared.

    If the input pin is in a non-latched state, a read of the input port register reflects the current port logic level. If the input pin is in a latched stated, then the read from the input register reflects the latched logic.

    In this scenario, when you enable the Bus Holder Register and the logic level at P0.0 is Low, you will always read 0. 

    Regards,

    Josh

  • 0
    Prodigy 140 points

    I am still confused about the latched input . I want to use this function for latching the input state , and when I read the register through the SPI then the interrupt should be cleared.

    Anytime when the input state changed , the input signal should be latched. when SPI read , the latched should be clear . 

  • 0 in reply to Bin Hu
    TI__Mastermind 37820 points

    Hello Bin,

    Let me configure the part to use the bus holder feature and share the results with you. 

    Regards,

    Josh