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TCA39306-Q1: I3C rise time issue after level translation

Bharati Aravatagi
Prodigy 60 points

Part Number: TCA39306-Q1

Hi,

I am using TCA39306DCURQ1 in our project for I3C level translation from 1.8V to 3.3V. We have designed circuit as per recommendation from datasheet.

image.png

But we see that SDA transactions are good before level translator with less rise time (+1V8 side) and go bad after level translator having more rise time (+3V3 side). 

image.png

Here yellow marled box is before level translator and red marked box is after level translator. 

Request you to help resolve the issue.

 

Thanks

Bharati

  • 0
    TI__Guru 62258 points

    Hi Bharati,

    The level translator is passive in its design and not a true I3C buffer. The output side will become high-z, and thus the pull-up resistor is the only source of pull-up current regardless if your I3C controller is in push-pull mode at the input.

    In order to achieve the logic high, you may need to adjust the pull-up resistors to be stronger (less resistance) so that the signal can rise to a VCC1 or VCC2 in time. Try using 2.2k PU resistors on each side of the level translator to see if there are any improvements. 

    Regards,

    Tyler

  • 0
    Prodigy 60 points

    Hi,

    We have tried different pull ups like 1.8K, 1.5K and 1.2K. 

    We see small difference in rise time with strong pull up's but not significant. 

    Does 200K pull up on Vref2/EN (R161) play role here? 

    Thanks

    Bharati

  • 0 in reply to Bharati Aravatagi
    TI__Guru 62258 points

    Hi Bharati,

    Was the change of PU resistors on both sides? It seems the I3C communication is being driven from the 3.3V side, stronger pull-up resistors on side 1 of the level translator would be most effective. 

    What changes from the controller side on the circled transactions? 

    Regards,

    Tyler

  • 0 in reply to Tyler Townsend
    Prodigy 60 points

    Hi Tyler,

    Pull up was changed on both sides to 1.5K. 

    Yes. 3.3V side is Master and 1.8V side is slave. Rise time issue is happening only in read transaction after repeated start. First circled transaction in CCC before repeated start. 8 clock cycle transaction has repeated start with slave read address. Only after this we see rise time issue.

    Thanks

    Bharati

  • 0 in reply to Bharati Aravatagi
    TI__Guru 62258 points

    Hi Bharati,

    So am I correct when saying that the second circled transaction is the data being sent from the target itself? It looks like the VOH of the target device is weaker than the VOH of the controller device. Thus it has a difficult time in the push-pull phase to drive a logic high at 12.5 MHz. 

    Do we have the specs of the slaves VOH/IOH vs. VOL/IOL or is it symmetrical? 

    Regards,

    Tyler