TCAN4550: Regarding the status during errors

Hello Ryu,

The TCAN4550 uses a FIFO on the SPI interface to handle the frequency domain crossing between the SPI clock domain used by the MCU and the high-speed clock (crystal) connected to the OSC1/2 pins that operates the digital core and MCAN controllers.

The MCU loads data into and pulls data out of the FIFO using the SPI clock.  Likewise the digital core loads data into and pulls data out of the FIFO using the high-speed clock.  The device also monitors the clock cycles to ensure the correct number of data bits are passing through the FIFO.  If an incorrect number of clock cycles are detected, then this results in either and Underflow or Overflow condition that is reported in the Status Register 0x000C.

There could be a couple of reasons for these bits being set.

The first is that the chip select is not remaining Low for the entire SPI read/write transaction.  It must remain Low for a minimum of 64 SPI clock cycles which would contain the Header word (read/write op-code of 0x41 or 0x61, Address, and Length fields) followed by the 32-bit data words.  Because multi-word read/write transactions are supported, the number of data words must match the value of the Length field in the Header word.  Therefore the number of SPI clocks in a SPI transaction = 32 + (Length * 32).

This type of error is more common during the initial development when the SPI driver is being developed to match the TCAN4550 protocol and format requirements.

The second reason you may be seeing bits 27-24 set is due to a physical disruption of the clocks.  If the SPI clock is correct, then the most likely issue is with the configuration of the high-speed clock (crystal) circuit. 

The TCAN4550 supports both a crystal and a single-ended clock on the OSC1/2 pins.  A voltage comparator is used on the OSC2 pin to check for a "grounded" pin by sourcing a small current and checking whether the voltage is less than 100mV (typ).  The actual threshold could range between 90-150mV across process, voltage and temperature conditions. When this is detected the device will disable the crystal current amplifier and use a mux to pass a single-ended clock to the digital core that is to be provided on the OSC1 pin.  If however, the OSC2 pin voltage is above the threshold, then the device will enable the current amplifier and source current to the crystal connected on the OSC1 pin and then take the input signal on the OSC2 pin to source the digital core.

However, if the crystal circuit is not optimized and the load capacitors and series dampening resistors that limit current to the crystal are not sized correctly, there is a risk of allowing the crystal to oscillate at a large level and create an oscillation waveform on the OSC2 pin with a large enough peak-to-peak amplitude that results in the lowest level of the waveform crossing below the single-ended detection comparator threshold and causes a momentary mode shift to the single-ended clock mode.  This will block the digital core and MCAN controller from having a valid clock so they are essentially paused until the oscillation amplitude decays and the device switches back to crystal mode.  If a SPI or CAN message occurs during this clock mode shift, then those messages will generate errors such as a SPI Underflow or Overflow error.

Please see the TCAN455x Clock Optimization and Design Guidelines Application Report (Link) for more information about optimizing the clock/crystal circuit.

If you do believe the SPI driver protocol is correct and this may be related to a clock/crystal issue, then the recommended solutions are as follows:

1. Add a series resistance (commonly referred to as a Dampening Resistor) between the OSC1 pin and the crystal.  This will reduce the amount of current flowing to the crystal and lower the peak-to-peak amplitude.  A common value to try is 30 ohms, but usually less than 100 ohms will suffice.

2. If a series dampening resistor is not an option, you can increase the capacitance value of each of the two load caps on the crystal.  For example, if they are each 8pF, you could increase them to 10pF to 12pF and retest.  This will cause a slight frequency shift due to the change to the overall load capacitance on the crystal.

3. To avoid a frequency shift, you can adjust the amount of capacitance on the OSC1 and OSC2 pins such that more of the capacitance is placed on the OSC2 side of the crystal and less is on the OSC1 side.  This creates a voltage divider effect with the reactance of the capacitance and the ESR of the crystal which lifts up the OSC2 voltage level but allows the total amount of load capacitance on the crystal to remain the same.

Regards,

Jonathan

Hi Jonathan,

Thank you for your reply.
Regarding the presumed cause 1, I believe it does not apply as it does not meet the conditions.
For cause 2, I will try the method you suggested.
A staff error is also occurring in CANFD. If it is the state described in cause 2, would this error occur?

Best Regards,
Ryu.

Hi Ryu,

Yes, this could be a possible cause because if the device switches away from the crystal to single-ended mode, an internal mux disconnects the crystal signal from being the clock source to the digital core and MCAN controllers.  Without a clock, the digital core and MCAN controller are effectively "paused" and will not be able to operate again until a valid clock signal is restored. Once the clock is restored, the operation will resume directly where it left off.

Therefore, If this clock disruption occurs during the middle of transmitting a CAN FD message, the MCAN controller will not be able to change the TXD bits and will hold the TXD bit whatever state it was in when the clock disruption occurred.  This could result in a pause for longer than 5 CAN FD bit times which would then be seen by other nodes on the bus as a Stuff Bit Error.

Regards,

Jonathan

Hi Jonathan,

Thank you for your reply.
Increasing the resistance or capacitance you provided eliminated the error.
However, when I inquired with the crystal manufacturer, they responded that the current constants are matched and increasing resistance or capacitance would be detrimental to oscillation.
Which approach should I follow?
The manufacturer recommends a circuit with Rd 0Ω and CIN/COUT 2pF, with a drive level of 80μW.

Best Regards,
Ryu.

Hi Ryu,

The crystal and the TCAN4550 have to work together in order to create oscillations and therefore a balance between the two component requirements must be achieved.  

The recommendations from the crystal manufacturer may be optimal for the crystal, but will not meet the needs for the TCAN4550 and prevent the OSC2 min level voltage from dropping below 150mV and creating a mode shift to the single-ended clock mode which will create the disruptions and errors you have observed.

The critical requirement for the TCAN4550 is to ensure that the OSC2 voltage remains above 150mV for all operating conditions to prevent the errors you have observed.  This requirement is not directly related to creating the optimal configuration for the crystal, but it is important if you do not want clock disruptions and errors.

Regards,

Jonathan

Hi Jonathan,

Thank you for your reply.
This has deepened my understanding.
I have one question.
Is there any way to confirm whether mode transition has occurred other than by measuring the OSC2 voltage?
I am attempting to measure the OSC2 voltage, but I'm unsure if my equipment is measuring it accurately. Therefore, I would like to know if there is a method to detect that mode transition has already occurred.

Best Regards,
Ryu.

Hi Ryu,

There is no direct method to monitor or detect this during normal operation.  But if you have the ability to connect a scope probe to the GPIO1 pin, then it is possible to use an internal test mode to monitor a divided down version of the internal clock that would show whether there was any mode shifts.  This is not something that can be used for normal operation but could be useful during your design evaluation. 

Do you have access to the GPIO1 pin?

Regards,

Jonathan

Hi Jonathan,

Thank you for your reply.

Jonathan Nerger said:

Do you have access to the GPIO1 pin?

Access to the GPIO pins is possible.
Could you please provide detailed instructions?

I measured the voltage at the OSC2 pin using an 1.8pF FET probe.
Although the measurement shows a less accurate waveform (with lower apparent amplitude) due to the probe's parasitic capacitance,
the peak voltage was found to be below 150mV.

・Reducing the amplitude too much may risk causing the device to stop oscillating, so please allow us to discuss the actual acceptable values.
Regarding boards without abnormalities, some units operate normally even when the peak value falls below the lower limit of 90mV. If you have data indicating the acceptable range of reduction as a practical value, would it be possible to share that?
・Is there a way to fix the oscillator mode instead of using automatic switching?

Best Regards,
Ryu.

Hi Ryu,

I have send you a private message with the procedure.  

The exact values a mode switch will occur will vary slightly from device to device and board to board due to manufacturing tolerance distribution between the various components in the circuits. 

The TCAN4550 also has an Automatic Gain Control (AGC) and Peak Detection circuit that will monitor the waveform on the OSC1 pin and try to adjust the amplifier output current to maintain an approximate peak-to-peak voltage amplitude of 1Vpp and a common mode voltage of approximately 0.7V. If the amplitude is less than 1Vpp, then the output current will be increased, and if it is greater than 1Vpp, then the output current will be decreased.  There is however a minimum amount of current that will always flow and the current level can't be reduced to zero.

The situation you are facing is that with a small external load connected between the OSC1 and OSC2 pins, the oscillation amplitude will become larger than 1Vpp even with the AGC outputting the minimum amount of current possible. If this occurs, the TCAN4550 can't regulate the amplitude.  Assuming the common mode voltage remains the same (such as at 0.7V) and increase in amplitude will have a higher Max peak voltage and a lower Min peak voltage.  If the lower peak voltage drops too low, the device can momentarily switch to single-ended clock mode thinking that the OSC2 pin has been "grounded."  This will disable the clock amplifier that stops sourcing current to the crystal which in turn will cause the amplitude to naturally decay.  Eventually the device will switch back to crystal mode and the the amplifier is re-enabled.  This can be a cycle if the loading conditions remain the same.

The only way to prevent this situation is to adjust the external components in the circuit between the OSC1 and OSC2 pins such that the circuit is operating within the AGC's min/max regulation window allowing it to maintain the proper 1Vpp amplitude for stable operation in crystal mode.

Unfortunately there is not a way to disable the single-ended clock mode detection circuit when using a crystal.  However, if you instead used a single-ended clock instead of a crystal, the OSC2 pin is grounded and effectively you can "fix" the device to single-ended mode, but you can't "fix" it into crystal mode.

You could consider using a LVCMOS Crystal Oscillator to create a single-ended clock instead of a crystal.  These come in similar size 4-pin packages to crystals and would remove the need to optimize the crystal circuit.

Regards,

Jonathan