TLK1501 synchronization and initialization problem.

hi..

My Board Structure.

ADC(Video, NTSC)-->FPGA --> TLK1501 -->SFP -------------------------------------- fiber ----------------------------------------- SFP-->TLK1501-->FPGA-->DAC(Video, NTSC)

Process about TLK1501 synchronization and initialization

1. FPGA Configration

2. TLK1501 TxClock 50MHz input(from FPGA), Enable is pull up, Loopen & PRBSEN is pull down.

3. 3 times(Txen = Txer = 0)

4. normal Operation(Txen = 1, Txer = 0)

but almost Link is fail.(somtimes Link is good)

what is the problem?

--------------------------- My source code ----------------------------------

 -- Data Transmit --
 process(GReset, SerdesClock)
 variable CntTx : integer range 0 to 10;
 begin
  if(GReset = '0') then  -- FPGA Reset
   CntTx := 0;
   OpticSync <= '0';
   SerdesTxData(9 downto 0) <= (others => '0');  -- Video
   SerdesTxData(12 downto 10) <= (others => '0');  -- Ethernet
   SerdesTxData(14 downto 13) <= (others => '0');  -- Audio
   SerdesTxData(15) <= '0';       -- Serial

  elsif falling_edge(SerdesClock) then
   if(OpticSync = '0') then
    case CntTx is
     -- IDLE State(3 times) --
     when 0 => SerdesTxEn <= '0';
        SerdesTxEr <= '0';
        CntTx := CntTx + 1;
        
     when 1 => SerdesTxEn <= '0';
        SerdesTxEr <= '0';
        CntTx := CntTx + 1;
        
     when 2 => SerdesTxEn <= '0';
        SerdesTxEr <= '0';
        OpticSync <= '1';
     
     when others =>
    end case;

   else -- Normal Operation
    CntTx := 0; 
    SerdesTxData(12 downto 10) <= EthRxDataBuf & EthRxDvBuf;
    SerdesTxData(14 downto 13) <= AudioAdcLrck & AudioAdcDout;
    SerdesTxData(15) <= VideoADC_Clock1;
    
    if(VideoADC_Clock1 = '1') then
     SerdesTxData(9 downto 0) <= VideoInputCh1;
    elsif(VideoADC_Clock2 = '1') then
     SerdesTxData(9 downto 0) <= VideoInputCh2;
    end if;
    
  end if;
 end process;