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Original question:

ESD601-Q1: S-Parameter

ESD601-Q1: ESD601-Q S-Parameter

haohao deng
Prodigy 20 points

Part Number: ESD601-Q1

I'm currently working with the ESD-01 TVS diode and analyzing its S-parameters. While the test circuit provided by the datasheet shows it in a series configuration, in my actual application, the TVS is connected in parallel — with either Pin 1 or Pin 2 tied directly to GND.
 
At RF frequencies, this parallel placement makes the TVS act as a low-impedance shunt, which severely attenuates the high-frequency signal and compromises signal integrity. This effectively renders it useless for protecting high-speed RF circuits, as the protection mechanism conflicts with the need for unimpeded signal transmission.
 

Question

 
Given this contradiction between the test setup and real-world RF application, how can I effectively utilize the ESD-01 for ESD protection in an RF circuit without degrading signal performance?
 
  • 0
    Prodigy 20 points
    about the S-parameter test setup for your ESD-601 device, as there appears to be a discrepancy between the test configuration and real-world application.
    According to the provided S-parameter data, the device is tested in a series configuration, where Pin 1 and Pin 2 are connected in series, and parameters like S11, S22, and S12 are measured. The datasheet also states that Pin 1 and Pin 2 are 50Ω matched under this test setup.
    However, in practical RF circuit designs, the ESD-601 is almost always used in a parallel configuration, with one pin tied directly to ground. This creates a significant mismatch between the test conditions and actual application. As a result, the S-parameters provided do not accurately reflect the device's performance in a real circuit, making it difficult to evaluate its impact on signal integrity and ESD protection effectiveness at high frequencies.
    Could you please clarify:
    1. Why the S-parameters are measured in a series configuration, rather than the parallel configuration that is standard for ESD protection?
    2. Can you provide S-parameter data measured under a realistic parallel (shunt-to-ground) setup?
    3. What is your recommended method for using the existing series S-parameters to simulate and predict performance in a parallel application?                              
  • 0 in reply to haohao deng
    TI__Genius 10410 points

    Hi Haohao, 

    ESD601-Q1 is almost always going to be used in a parallel configuration so ESD events have a path to ground (can be seen in image below). 

    When we collect our s-parameter data, we use our ESD EVM. The schematic is shown below. One pin is connected to ground and the other is connected to both ports. 

    When I run both simulations you have shown above, the left hand one shows what I expect for S21. When I run the right hand side and select S21 to show, I am getting what I would expect for S11. Based on this, I believe the left hand simulation image is correct. 

    Best,

    McKenzie

  • 0 in reply to McKenzie Eaker
    Prodigy 20 points

    Hi，McKenzie：

      I want to say if using the left simulation circuit,how to protect  circuit?


      Hower,even it will change impedence of port1/2 if using the right simulation.The signal of the port1 is not tranferfed to the port1,as below

  • 0 in reply to haohao deng
    TI__Genius 10410 points

    Hi Haohao, 

    The image below looks like the termination is connected to both pin 1 and pin 2 of the device but this is a misunderstanding. When the s-parameter data is collected, pin 2 of the device is connected to ground while pin 1 is connected to a two port system. This then follows the image below. The ground connection would be pin 2 with the two port connections (the two terminations) going through pin 1. 

    When you protect the device in a circuit, you would follow the schematic below. 

    Best,

    McKenzie