TMS320C6747: Concerns about using MRAM with the TMS320C6747

Hello Keisuke Ikemori-san,

Thank you for your query !

I'll need to discuss your questions with the TMS320C6747 EMIF topic owner / expert tomorrow.

Please expect that some delay in our response is possible.

We appreciate your patience !

Thanks

Kind Regards,

Anastas Yordanov 

Hello Keisuke Ikemori-san,

First I would like to apologize for the big time gap in my response !

Keisuke IKEMORI said:

Q1: Is it possible to use this MRAM as 16-bit asynchronous memory on EMIFA?

A1. "It does appear that MR5A16AUMA45 would work, at least from a pin connection perspective."

Please expect my follow-up to additionally confirm on the electrical and timing parameters compliance.

Keisuke IKEMORI said:

Q2: Can RBL boot from this MRAM in EMIFA NOR boot mode?

A2. "MRAM is not listed as a supported boot mode in the Chapter, Boot Considerations / Section, Introduction of the TMS320C6747 TRM 

Keisuke IKEMORI said:

Q3: Are there any known issues when sharing the EMIFA bus with an FPGA?

A3."I am not aware of any as long as different CS signals are used."

Keisuke IKEMORI said:

Q4: I'll use a separate NOR Flash for booting, but I'll use the MRAM as external work memory connected to EMIFA.

Are there any restrictions or conflicts when using NOR Flash (for boot) and MRAM (for data) simultaneously with different chip selects?

A4: "This appears to be a standard setup as shown in the Chapter, External Memory Interface A (EMIFA) / Section, Example Configuration of the TRM."

Please expect my follow-up by end of this week.

Thanks for your understanding !

Best Regards,

Anastas Yordanov 

Hello Keisuke Ikemori-san,

I would like to sincerely apologize for the big time gap in my response on the electrical and timing parameters compliance.

According to the TMS320C6747 Datasheet rev. F  (SPRS377F) - Magneto-resistive RAMs are NOT officially stated as supported memory type by the DSP EMIFA HW interface.

Both, the two-die MR5A16A memory + TMS320C6747 EMIFA controller support an asynchronous interface, 16-bit wide data bus and 15-bit row/column address bus, 3.3V LVCMOS logic.

However the MR5A16A memory  address, control and data inputs defined max capacity Ci = 8pF is greater than the maximum allowed TMS320C6747 LVCMOS EMIFA outputs capacity of 3pF used for AC timing measurement characterization. This means, there is a risk that the EMIFA timing parameters documented in the Datasheet at Cout_max  = 3 pF during EMIFA characterization may not be met even under nominal conditions, as soon as MR5A16A input pins (max 8 pF) are attached.  

To this potential timing compliance issue I would also like to point out that I could not find any data that the non-TI MR5A16A was tested / used with TMS320C6747 EMIFA interface.

Please let me know in case you have more questions.

Thanks

Best Regards

Anastas Yordanov