Part Number: DP83867CR
Hello-I’m using a third-party board with a Zynq Ultra Scale + (ZU19EG) with a TI DP83867CR Ethernet PHY. I’m using the AMD TEMAC IP for 10/100/1000 Mb/s ethernet. The settings on TEMAC are 1Gbps, RGMII Tri-Speed, MDIO selected for AXI4-LITE at 125MHz, logic is in example design all other features are turned off.
I can’t get the TI PHY to AN to anything but 10Mb/s. I have connected over CAT5E cable a 1Gb/s ethernet BERT that will AN with any 10/100/1000 Mb/s ethernet device. The strappings on the board are:
PHY_ADD0 = 0
PHY_ADD1 = 0
PHY_ADD2 = 0
PHY_ADD3 = 1
Autoneg Disable = 1
RGMII Clock Skew TX[0] = 0
RGMII Clock Skew TX[1] = 0
RGMII Clock Skew TX[2] = 0
ANEG_SEL = 0
Mirror Enable = 0
RGMII Clock Skew RX[0] = 0
RGMII Clock Skew RX[1] = 0
RGMII Clock Skew RX[2] = 0
I modified the AMD/Xilinx AXI FSM (VHDL) to use the extended addressing on the PHY. The MDC I’ve set to 2.5MHz, 2MHz and 100kHz. Only 2.5 and 2MHz will AN at 10Mb/s. The following are the registers I set and the order I set them. Are they out of order or do I need to do something different to get the PHY to AN at 1Gb/s?
Read BMSR, if not xFFFF continue
Set CFG3=> x0680 (also tried x0280)
Set ANAR=> x01e1
Set CFG1=> x0200
Start Extended Addressing:
Set REGCR=>x001f
Set ADDAR=>x0032
Set REGCR =>x401F (data mode)
Set ADDAR=>x00D3 (enable RGMII, TX/RX delays)
Set REGCR=>x001f
Set ADDAR=>x0086 (RGMII CTL)
Set REGCR =>x401F (data mode)
Set ADDAR=>x00A8 (Tx Delay 2.75ns, Rx Delay 2.25ns per the manf. Of the board)
Set BMCR=>x1340 (enable AN, Restart AN, speed ’10’=1000Mb/s)
Set PHYCR=>xc440 (Tx FIFO 8B, Force Link Good, enable auto crossover MDI)
Is this the correct order to enable AN at 1000Mb/s? Thank you.
