DP83867CS: minimum length of IPG

Danilo

DP83867 supports the expected 12 byte IPG at the MDI as well as lower amounts in some conditions. This number comes from IEEE802.3 section 4.4.2 which sets out that the minimum IPG for a transmitted frame is 12 bytes on the TX lines of the MAC. When the data comes to a PHY, there is a handoff of clocking domains and thus there is potential for IPG to be 11 bytes when sent on MDI line. In cases where the IPG is smaller, Reg 0x53[3:0] can help increase margin in these applications with no drawback on performance. The lowest that this can be set is to 0x3 (default is 0x5) which has been seen to support 11 IPG. Setting to 0x4 is also sufficient.

Thanks

David

Hello David,

this is the first project where we use the DP83867CS. In all our previous projects we have used the Marvell 88E1512 Phy and we had no problems at all.
But with the DP83867CS we get an unstable link if we go over some hops.
We don't have any problems if we exchange the DP83867CS by an 88E1512 in the same project.

The DP83867CS is working fine in a point to point application but with some hops inbetween we can't get it stable.
I have tried all possible settings in reg. 0x53 already but it didn't help.

It is working if I increase the IPG lenght in that application. But we can't do that because of backward compatibility.

Is there anything else what I can test or are there some other register settings which could help?

Thanks
Andreas

Andreas

"The DP83867CS is working fine in a point to point application but with some hops in between we can't get it stable", are you seeing the link not being stable or packet error? The IPG typically associated with packet error issue, not necessarily a link drop issue, so I am trying to understand the exact issue you are seeing.  

Is it possible to share your schematic? When you add hops between the DP83867CS, are they just PHYs?

Thanks

David

Hi David,

we are using SGMII interface. I can't measure RX_CTRL because RGMII interface is disabled.
The hops are PHYs with SGMII interface connected over a crosspoint switch.
Each PHY has its own free running crystal as reference clock. That is the asynchronous part.

I am still investigating and read the link quality registers and error counters tomorrow.

This is our IPG sequence:

Hi David,

after several loop back tests I found out that there is a problem on the SGMI side.

I couldn't find any specific electrical caracteristics for the SGMII interface in the data sheet like differential Vpp .

Please give me the electrical specifications for the SGMII interface.

Thanks
Andreas

Andrea

Please see below for the SGMII spec, you can download the latest version from Cisco.

SGMII_1.7.pdf

Thanks

David