AM623: AM623x OSPI sustained throughput with DMA at 50 MHz (Octal SDR)

Hello Shaik,

Thank you for your query !

Q1. Would you please clarify which type of Octal SPI-NOR FLASH memory is emulated by the FPGA (like S28HS512T or other).

Q2. What type of command-address-data access protocol is used (like 1S-1S-8S,etc.)

Thanks

Best Regards

Anastas Yordanov

Hi Anastas,

1. We are trying to emulate Micron MT35XU512ABA1G12-0AAT.

2. We plan to use an 8S-8S-8S, SDR access protocol in memory map mode

During the initial probe , the device will start in 1S-1S-1S for JEDEC/SFDP, and then switch to 8S-8S-8S SDR for streaming.

Hi Shaik,

Thank you for your prompt and detailed response !

Sorry but I forgot to ask you few more questions:

Q3: Can you precise the method of OSPI RX sample clock generation - TAP mode (no loopback) or PHY mode (with a loopback of the OSPI0_CLK).

Q4. If it is a PHY SDR mode, considering the constraints in the Section, OSPI  of the AM623 Datasheet and OSPI related Advisory notes from the AM62x Silicon Errata, please precise the OSPI0 clocking topology according to the Section, OSPI/QSPI/SPI Board Design and Layout Guidelines of the AM623 Datasheet.  

Q5: Which OS - (U-Boot/Linux or MCU PLUS RTOS)  and TI SDK version are you talking about ?

Thanks

Best Regards,

Anastas Yordanov

Hi Anastas,

3. We are using a TAP mode (no loopback) .

4. Board routing is designed to meet the routing requirements.

5. We are using ti-linux-6.6.y

Regards,

Nazeer

Hello Shaik,

Shaik Mahaboob Nazeer said:

What sustained payload throughput (MB/s) is realistically achievable on AM623x OSPI under the above conditions?

Thanks for these initial clarifications. Based on them I am currently trying to reach out to a TI SDK Linux OSPI driver software expert in benchmark tests of OSPI Flash memories, who could possibly answer your question  for the FPGA emulated Micron MT35XU512ABA1G12-0AAT. 

Shaik Mahaboob Nazeer said:

Any recommended OSPI/DMA configuration best practices to maximize sustained read throughput?

I think from OSPI hardware interface perspective, you shall try to increase the OSPI0_CLK (up to 166 MHz possible), using PHY DDR mode with a DQS loopback clocking topology. A PHY data tuning algorithm shall be ultimately applied to achieve stable operation at higher than 50 MHz frequencies. At 166 MHz, 1.8V power supply, octal DDR mode, 8D-8D-8D, it shall be possible to theoretically achieve data read rates ~ 166*10^6 Hz*2 / (1000*1000) s^-1  = 332 MB/s.  To achieve high speeds with OSPI0_CLK frequency exceeding several tens of MHz, you shall take into consideration all TI recommended PCB High-speed Layout rules for OSPI hardware implementation ! 

Please expect that some delay in software expert response is possible. Please ping this thread if you don't get the answer by mid of the next week ! 

Thanks for your patience !

Best Regards

Anastas