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TIOS102: TIOS102 VCC(min) Behavior

Akeem Kennedy
Prodigy 20 points

Part Number: TIOS102

I’m evaluating the TIOS102 for an application, and I need clarification on the device’s VCC(min) specification and how it relates to the internal P‑channel FET structure.

According to the datasheet, VCC(min) is 4.75 V. However, based on the simplified internal diagram, VCC appears to connect directly to the source of the internal P‑channel MOSFET. In principle, if:

VDS>(VGS−VTH)

the P‑channel should still be able to pass the source voltage through to the OUT pin, even if the source is significantly lower than 4.75 V.

My application:

I am trying to use the TIOS102 to pass a ramping voltage that varies continuously from 0 V to 21 V. Essentially, VCC itself will be swept across that full range, and I want OUT to follow it.

However, if the device requires VCC ≥ 4.75 V to operate, then the ramp would not begin passing through until 4.75 V — which is not acceptable for my design.

My questions:

  1. What is the actual reason VCC(min) is specified at 4.75 V?
    Is this due to internal control logic, gate drive requirements, internal LDOs, or something unrelated to the P‑FET structure?

  2. If VCC is below 4.75 V (for example 2 V), will the device still behave like a simple pass FET, or will the output be blocked even though the MOSFET physics would normally allow conduction?

  3. Is the TIOS102 fundamentally incapable of passing voltages below 4.75 V, or is the datasheet minimum strictly related to the protection/control circuitry (e.g., status reporting, fault detection)?

Goal summary:

  • Need to pass a 0–21 V analog ramp through a push-pull output.
  • OUT must follow VCC all the way down to ~0 V.
  • Looking for clarification on whether the TIOS102 can support this, or if another TI device would be more appropriate. If it starts at 2V that would be acceptable.

Attached is an image showing the kind of ramp waveform I need to reproduce.
image.png

Thanks in advance for your help.

  • +1
    TI__Mastermind 35410 points

    Hello Akeem,

    Akeem Kennedy said:
    What is the actual reason VCC(min) is specified at 4.75 V?
    Is this due to internal control logic, gate drive requirements, internal LDOs, or something unrelated to the P‑FET structure?

    I addition to being connected to the PFET in the driver stack, the VCC supply pin is used as the source for the internal LDOs needed to operate the digital portion of the device.  The low voltage VCC_IN pin does not power the digital core and is only used as the voltage reference for the digital IO level shift circuits.

    Akeem Kennedy said:
    If VCC is below 4.75 V (for example 2 V), will the device still behave like a simple pass FET, or will the output be blocked even though the MOSFET physics would normally allow conduction?

    If device will enter a protected under-voltage lockout state when the VCC supply voltage falls below the V(uvlo) threshold which disable the output driver and digital interface.

    Akeem Kennedy said:
    Is the TIOS102 fundamentally incapable of passing voltages below 4.75 V, or is the datasheet minimum strictly related to the protection/control circuitry (e.g., status reporting, fault detection)?

    The device is designed to work with a minimum VCC voltage of 4.75V.  It is not designed to output a voltage on the OUT pin when the VCC voltage is less than 4.75V and will treat this as an under-voltage condition and disable the driver.  Therefore, I would say yes, the device is not capable of passing voltages less than 4.75, and does not seem capable of producing your voltage ramp between 0V and 4.75V.

    The TIOS102 would only be able to support a ramp between 4.75V to 21V.

    Regards,

    Jonathan