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DS110DF111: XFI to SFI

Part Number: DS110DF111

Hi team,

Could you support following questions?

[Q1]

Do you have any register profiles or configuration documentation for this device? We plan to use this device for XFI to SFI conversion.

[Q2]

Regarding VRX-LAUNCH (SourceTransmitSignalLevel), is my understanding below correct? Please point out any inaccuracies.

"This represents the recommended output level of the IC (e.g., CPU's TX) connected to the RX of the DS110DF111. The input level at the RX pin only needs to be 20mVpp or higher as specified by SDH. The VRX-LAUNCH value of 600-1600mVpp is calculated anticipating losses due to the trace between the DS110DF111 and the CPU, and is not a mandatory requirement."

Best regards,
Goto

  • Hi Goto-san,

    Please see answers below:

    [A1]

    Yes, we have configuration information in the data sheet and in programming guide below.  We also have SigCon Architect GUI for this device.

    https://www.ti.com/lit/pdf/snla323

    A few key things to set:

    1. Adapt mode
    2. CDR lock rate (In your case, default of 10.3125 Gbps is good)
    3. TX Settings

    [A2]

    I think your understanding here is mostly correct, but I would like to clarify a few things.

    This represents the recommended output level of the IC (e.g., CPU's TX) connected to the RX of the DS110DF111.

    Yes, this is correct.  The VRX-LAUNCH represents the recommended output level of the link partner TX (e.g. CPU's TX) that is connected to RX of DS110DF111.

    The VRX-LAUNCH value of 600-1600mVpp is calculated anticipating losses due to the trace between the DS110DF111 and the CPU, and is not a mandatory requirement.

    Yes, this is correct.

    The input level at the RX pin only needs to be 20mVpp or higher as specified by SDH.

    It is correct that >= 20mVpp signal is required for "Signal Detect" (SD) to be ON.  I want to clarify that Signal Detect is responsible for powering on a channel when a signal is detected.  Meeting signal detect criteria is not necessarily representative of system BER.

    In a high speed application, the signal sent by the link partner TX (e.g. CPU's TX) will be attenuated by the insertion loss of the channel.  Since insertion loss is frequency dependent, the lower frequency content in the signal will not be attenuated as much as the higher frequency content of the signal.  Because of this, I think it is unlikely that real data transmitted at 600mVpp would be received at 20mVpp.  The amplitude at the receiver would most likely be >20mVpp

    Thanks,

    Drew