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Reference clock for CPU and PHY

Giuseppe Modugno
Prodigy 70 points
Other Parts Discussed in Thread: DP83848C, CDCVF2505

I'll use DP83848C Ethernet PHY from National Semiconductor and Kinetis K60 microcontroller from Freescale with integrated Ethernet MAC peripheral. I'll use RMII mode.

After reading some docs, I understood that the main reference clock must be 50MHz and must be the same for MAC and PHY. I'm asking if I can use 25MHz_OUT signal output from PHY to give the clock to the CPU (so to the MAC too). In AN-1405 I read:

The  25MHz_OUT  signal  is  a  delayed  version  of  the  X1/
REF_CLK  input.  While  this  clock  may  be  used  for  other
purposes, it should not be used as the timing reference for
RMII control and data signals.

So I think this signal can't be used to synchronize CPU.

The 50MHz oscillator is from AKER, S7 series. Could I connect the output of this oscillator at the same time to PHY and CPU clock input?

  • 0
    TI__Mastermind 31600 points

    The DP83848 25MHZ_OUT pin should not be used as the RMII reference clock to the MAC.  The timing of this clock relative to the RMII data interface cannot be guaranteed.  This connection will most likely result in data errors, probably receive CRC errors in the MAC.

    The 50MHz oscillator can be used as the source for both the PHY and the MAC.  The PHY is not designed to handle a modulated clock so it is important to choose an oscillator without spread spectrum clocking. 

    Using a clock buffer to drive the clock inputs independently would be considered best practice.  One possible choice of clock buffer would be the TI CDCVF2505 (http://www.ti.com/product/cdcvf2505). 

    If you choose to connect the oscillator directly to the PHY and the MAC without a clock buffer, simulating the signal integrity using IBIS models is recommended.  Using series terminations in the traces is often beneficial. 

    Further recommendations on RMII traces are available in the Design and Layout Guide, AN-1469 (http://www.ti.com/litv/pdf/snla079c).  Specific recommendations are quoted below:

    • It is recommended to keep the signal trace lengths as short as possible. Ideally, keep the traces under 6 inches.
    • Trace length matching, to within 2.0 inches on the MII or RMII bus is also recommended. Significant differences in the trace lengths can cause data timing issues.
  • 0 in reply to Patrick OFarrell
    Prodigy 70 points

    Patrick O'Farrell said:
    The 50MHz oscillator can be used as the source for both the PHY and the MAC.  The PHY is not designed to handle a modulated clock so it is important to choose an oscillator without spread spectrum clocking.

    I'm sorry for the dumb question, but how can I understand if the oscillator has or hasn't "spread spectrum clocking"? I couldn't find any parameter related to frequency modulation or similar in the datasheet of my oscillator.

    Patrick O'Farrell said:
    Using a clock buffer to drive the clock inputs independently would be considered best practice.  One possible choice of clock buffer would be the TI CDCVF2505 (http://www.ti.com/product/cdcvf2505). 

    Thank you for your suggestion.

  • 0 in reply to Giuseppe Modugno
    TI__Mastermind 31600 points

    Sorry for introducing the confusion.  When I checked the Akers clock oscillator web site, I saw that the S7 series has a Low EMI family that includes spread spectrum clocking.  I wanted to make sure that you were not intending to use a part from that family.

    Spread spectrum clocking would be called out in the datasheet.  Typically the spread would be specified.  You can see an example of this in the Akers S7 Low EMI datasheet (http://www.aker-usa.com/Clock_Specs/S7%20Low%20EMI%20General%20Specification.pdf). 

    The Akers S7 General Product Specification (http://www.aker-usa.com/Clock_Specs/S7%20General%20Specification.pdf) looks fine.  These oscillators do not have spread spectrum clocking.

  • 0 in reply to Patrick OFarrell
    Prodigy 70 points

    Patrick O'Farrell said:
    Sorry for introducing the confusion.  When I checked the Akers clock oscillator web site, I saw that the S7 series has a Low EMI family that includes spread spectrum clocking.  I wanted to make sure that you were not intending to use a part from that family.

    Dear Patrick, thank you very much for wasting your time with me. I really appreciate.

    My company already uses a Ultra-High Speed dual buffer from Fairchild NC7WZ16P6X. It has very low propagation delay and high driving capacity on its outputs. Do you think it could be a good solution to distribute the 50MHz clock from Aker oscillator to DP83848C and CPU?

  • 0 in reply to Giuseppe Modugno
    TI__Mastermind 31600 points

    Giuseppe,

    You are not wasting my time.  I am here to help and I am glad to do so. 

    The Fairchild NC7WZ16P6X looks like a suitable clock buffer.  The main difference I see is that it is not a PLL clock driver like the TI CDCVF2505.  That should not be an issue because aligning the phase of the output clocks to the input clock is not a requirement in this application.

    Please note that the NC7WZ16 datasheet does not specify skew between the output clocks.  I would recommend confirming the skew with Fairchild. 

    For the R/MII signal traces, we recommend matching lengths to within 2 inches.  Assuming 167 ps per inch propagation delay across FR4, that translates to a worst case skew of 334 ps.  I would suggest that value as an upper bound for skew between the clocks. 

    Of course, less skew would be better.  Skew between the reference clocks will just reduce the R/MII timing margin.  

    Patrick