Part Number: TMS320C6746
Based on the datasheet, it appears that using VTT as specified by JESD79-2 is not recommended.
I am uncertain whether to design the hardware using only series termination without a termination IC.
Your advice would be appreciated.
Figure 6-18. DDR2/mDDR Single-Memory High Level Schematic includes the following note regarding termination settings:
Place termination resistors as needed. Refer to the note regarding termination resistors.
The section regarding termination is:
.4.4.3 DDR2/mDDR
• Parallel termination is not allowed on CLKP/CLKN pins.
• If termination is used, the DDR2/mDDR drive strength should be set to full strength. Otherwise, the
drive strength should be set to half strength.
• No pullups or stubs are allowed on any DDR pins.
• For DQS and D net classes:
– Routes must be point-to-point. – Skew matching across bytes is not needed nor recommended. – Skew between the two classes should not exceed 25 mil.
• Clock and DQS net class trace lengths need to be routed such that the skew between the two net classes meets the tDQSS timing parameter.
6.11.3.9 DDR2/mDDR Signal Termination
No terminations of any kind are required in order to meet signal integrity and overshoot requirements. Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only type permitted.
Please advise how to interpret the above.
