DP83826E: phy(DP83826) to phy(DP83826) connection without transformer

Hi,

Can you please share your schematic for review? 

Are you using one set or two sets of capacitors between DP83826? Is it possible that you can change the capacitor from 0.1uF to the recommended 33nF? 

Thanks

David

There are one set of capacitors between DP83826.

I paid for 33nF capacitors, but it didn't arrive.

With the capacitors kept in place, the transmission and reception tests with the PC functioned normally when the RJ45 connector was soldered to the DP83826_TD/RD net.

(The opposite board (dp83826) has no capacitor on the signal line)

Hi,

Are you leaving DP83826 strapping in their default state?

With a PC, I would imagine it is a transformer design with a different PHY. When connecting to the 2nd DP83826, can you please probe on the capacitor? Are you seeing the link pulse being sent by either DP83826?

Thanks

David

One board is configured with an MII interface, while the other is connected via RMII. The image below shows the strapping configuration for the DP83826 using the MII interface. I have already verified that the strapping is correctly applied by reading the registers through MDIO.

I also checked with the oscilloscope that there is a link pulse.

Hi

For the MII interface design, I don't see an issue with the strapping configuration. 

Since you have MDIO access, can you please dump out the register 0x00 to 0x1F, 0x467, and 0x468 when the two DP83826 are connected? Please note 0x467 and 0x468 are extended registers and require to use the extend access to read these two registers. 

Can you also share the scope waveform of the link pulse? 

If you change the 2nd DP83826 from RMII to MII, are you able to link up?

Is the DP83826 RMII board able to link up with the PC?

Thanks

David

The registers are being strapped normally as I intended.

PHY 1: BMCR = 0x3000
PHY 1: BMSR = 0x7849
PHY 1: PHYIDR1 = 0x2000
PHY 1: PHYIDR2 = 0xa111
PHY 1: ANAR = 0x00a1
PHY 1: ANLPAR = 0x0000
PHY 1: ANER = 0x0004
PHY 1: ANNPTR = 0x2001
PHY 1: ANNPRR = 0x0000
PHY 1: CR1 = 0x0020
PHY 1: STS1 = 0x0102
PHY 1: 1KSCR = 0x0000
PHY 1: PHYCR = 0x8001
PHY 1: SOR1 = 0x0497
PHY 1: SOR2 = 0x119d

2nd dp83826 cannot be modified because the wiring is RMII.

I will share the link pulse as soon as it is confirmed, but is there any solution as it is?

Hi,

Is the RMII board able to link up with a PC?

If both the MII board and RMII board able to send link pulse, then I would expect both board able to link up. My only concern on the RMII is that we have RMII Leader and RMII Follower with different clock implementation. If clock implementation does not follow RMII Leader or Follower mode, then it would not able to link up.

Thanks

David

RMII board does not link up with PC and repeats link up/down.

------ log -------

Cpsw_handleLinkUp: Port 1: Link up: 100-Mbps Full-Duplex
MAC Port 1: link up
[0] link_callback==UP
[1] link_callback==UP
Cpsw_handleLinkDown: Port 1: Link down
MAC Port 1: link down
[0] link_callback==DOWN
[1] link_callback==DOWN
Cpsw_handleLinkUp: Port 1: Link up: 100-Mbps Full-Duplex
MAC Port 1: link up
[0] link_callback==UP
[1] link_callback==UP
Cpsw_handleLinkDown: Port 1: Link down
MAC Port 1: link down
[0] link_callback==DOWN
[1] link_callback==DOWN
Cpsw_handleLinkUp: Port 1: Link up: 10-Mbps Full-Duplex
MAC Port 1: link up
[0] link_callback==UP
[1] link_callback==UP
[0]status_callback==UP, local interface IP is 169.254.244.236
[1]status_callback==UP, local interface IP is 169.254.229.236
------------------

Given that it's connected at 10 mega speed as above, isn't it probably a clock problem?

My current clock configuration is as follows:

*Source: 50MHz from AM2431_ALV CLKOUT0 (Pin U13) – verified normal output.

*Path: Input to LMK1C1104PWR (CLKIN), then distributed to:

 - AM243 RMII_REF_CLK (Pin AA5)

 - DP83826 XI (Pin 9)

*Measured Voltage: Approximately -0.25V to 3.8V.

(3.3v is being supplied to VDDIO of DP83826)

Hi,

For this register dump,

Is this the dump from the MII or the RMII board? From the dump, it looks like it is a RMII board dump? 

From the dump, you are configuring the PHY as 100M with Half Duplex, does this match with your design requirements? Can you change to full duplex?

Thanks

David

Register dump when set to half-duplex.

PHY 1: BMCR = 0x3000
PHY 1: BMSR = 0x7849
PHY 1: PHYIDR1 = 0x2000
PHY 1: PHYIDR2 = 0xa111
PHY 1: ANAR = 0x00a1
PHY 1: ANLPAR = 0x0000
PHY 1: ANER = 0x0004
PHY 1: ANNPTR = 0x2001
PHY 1: ANNPRR = 0x0000
PHY 1: CR1 = 0x0020
PHY 1: STS1 = 0x0102
PHY 1: 1KSCR = 0x0080
PHY 1: PHYCR = 0x8001
PHY 1: SOR1 = 0x0497
PHY 1: SOR2 = 0x119d

Register dump when set to full-duplex.

PHY 1: BMCR = 0x3100
PHY 1: BMSR = 0x7849
PHY 1: PHYIDR1 = 0x2000
PHY 1: PHYIDR2 = 0xa111
PHY 1: ANAR = 0x01e1
PHY 1: ANLPAR = 0x0000
PHY 1: ANER = 0x0004
PHY 1: ANNPTR = 0x2001
PHY 1: ANNPRR = 0x0000
PHY 1: CR1 = 0x0020
PHY 1: STS1 = 0x0102
PHY 1: 1KSCR = 0x0080
PHY 1: PHYCR = 0x8001
PHY 1: SOR1 = 0x0496
PHY 1: SOR2 = 0x119f

The same situation happened when I changed the setting to full-duplex as above

Maybe the front end is broken.
I tested it with a different board and it's 100Mbps full-duplex link up.

However, I did a ping test from PC to the board, but there is no response.

The RMII board receives ARP messages and calls up to ethernet_output(), but does not check packets in wireshark.

Hi,

This is not a PHY issue, but more a configuration issue with the Wireshark.

Thanks

David