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DS90UB960-Q1: DS90UB960: Rear camera RAW+YUV causes repeated frames with 4 cameras enabled — need full analysis support

Part Number: DS90UB960-Q1

Hi TI team,

We need detailed support regarding a stability issue with DS90UB960 + DS90UB953 in a 4-camera configuration.

System Configuration

  • Deserializer: DS90UB960

  • Serializers: DS90UB953 (4 ports used)

  • 3 cameras: YUV422 8-bit

  • Rear camera: Simultaneous RAW + YUV output

  • Resolution/FPS: ~1790 × 1163 @ 30 fps (VTS ~1231)

TI deserializer team previously reviewed this configuration and confirmed via bandwidth calculation that this setup should be supported.

Observed Behavior

When all 4 cameras are enabled:

  • The rear camera (RAW + YUV) does not freeze completely,
    but displays repeated frames / short looping behavior (“boomerang effect”).

  • The other 3 YUV cameras remain stable.

  • If we disconnect any one camera, the remaining cameras work correctly.

  • If the rear camera is configured as YUV-only, the system is fully stable with all 4 cameras connected.

This issue occurs consistently and is reproducible.

Our Understanding

The issue appears only when the rear camera outputs both RAW and YUV simultaneously along with the other 3 YUV cameras. It seems frames are being dropped or reused internally when RAW is enabled.

There are no obvious physical link issues observed.

Support Requested from TI

We request TI’s full support to analyze this issue in detail.

Specifically:

  1. Please confirm whether this exact configuration (3x YUV + 1x RAW+YUV) is fully supported in DS90UB960 under the given resolution/FPS.

  2. Please advise if there are:

    • Special forwarding requirements

    • Virtual channel mapping recommendations

    • Data type handling constraints when RAW + YUV are active together

    • Known limitations in buffering/scheduler behavior

    • RAW format constraints (RAW10 vs RAW12, packed vs unpacked)

  3. Please provide guidance on:

    • Which DS90UB960 registers we should monitor to identify overflow/packet drops

    • Any debug procedure to confirm CSI TX packet drop or internal FIFO saturation

Since TI previously confirmed via calculation that this configuration should work, we would appreciate a detailed technical review to understand why this behavior is occurring in practice.

We require TI’s assistance to reach a stable production configuration.

Thank you,

Pratham.

  • Bandwidth calculation earlier made by TI, Attaching just fyr.

  • Hi Pratham,

    Thanks for this info, do you have any of the info below?

    1. Do you have a register dump in the failing scenario? Buffer overflow is shown in register 0x4E[4].
    2. For the calculator where the bits per pixel is 28, is this 16bpp YUV422 + 12 bit RAW? If so, how is this data sent on the CSI-2 interface? Will RAW and YUV lines come separately?
    3. Could you bring out line valid & frame valid to GPIOs for RX0 to check total vertical lines? Active lines and line length can also be verified in registers 0x73-0x76.

    The UB960 does not have a frame buffer, and is unable to re-transmit CSI-2 long packets. 

    Best,

    Thomas

  • .  This is all the deserializer dump,(00-FF) . main page registers after switching to dual mode
  • Hi Pratham,

    Could you please provide register dump for RX0 with mixed mode camera? 0x4C should be set to 0x01 to get this register dump.

    Best,

    Thomas

  • Hello Thomas ,

    We are seeing that UB960 register 0x4C is toggling . We also tried forcefully writing 0x01 to 0x4C, but the value changes again on subsequent reads (it continues to toggle between values such as 0x12, 0x38, 0x24, and 0x01).

    Could you please confirm if 0x4C is expected to be updated automatically by internal state (e.g., port selection/link status)? 

    These are our deserialzer settings  in our software .port0 is corresponding to rear, that is why we have set 0x4c to 0x01.

     

  • Hello Thomas,
    We have one observation with (73-76 register) as you have asked me to read

    1. We use imager register 0x2498 as the confirmation of the sensor stream configuration:

    • 0x2498 = 0x70 → single stream (YUV only)

    • 0x2498 = 0xF2 → dual stream (RAW + YUV)

    1. We switch single → dual using the following I2C group writes (all return “Register write successful”):

      b 0 3 9002 1 83
      b 0 3 9003 1 02
      b 0 3 9004 1 00
      b 0 3 9005 1 01
      b 0 3 9006 1 01
      b 0 3 1760 1 01

    2. After the switch, we repeatedly read:

      0x2498 (imager)

      0x73, 0x74, 0x75, 0x76 (TI requested)

      What we observe

      • After the group writes, 0x2498 always reads 0xF2 on every read (so the sensor remains in dual stream continuously).

      • Even while 0x2498 stays at 0xF2, the TI-requested registers 0x73–0x76 are not stable:
        0x73/0x74 values toggle between two sets repeatedly during streaming (see log screenshot).

      So we have a mismatch:

      • Sensor-side mode proof (0x2498) is stable = 0xF2

      • 0x73–0x76 are toggling during the same time window

      Why do 0x73–0x76 toggle like this even though the sensor remains in dual-stream (0x2498=0xF2) continuously?
      Thanks ,

                Pratham

  • Hi Pratham,

    The register 0x4C will not toggle based on any internal function of the device, status will only change based on 0x4C based on I2C writes to the ser. Do you know if register 0x4C is still toggling during this test? 

    Assuming 0x4C is stable, I'm curious what it means for the sensor to be streaming two video types at the same time. Is this this consecutive frames? consecutive video lines? Consecutive pixels? If this is consecutive frames, these registers would update by each frame as they are set after each frame. If this is each line, we should see a higher line count for each frame. If this is by pixel, we should see the line length is higher than expected.

    Best,

    Thomas

  • Hello Thomas,

    This is a frozen video for your reference. I’ve already sent the register dump for 0x4C to Katie via email, since I’m not able to upload it here due to the file format restrictions.

  • Hi Pratham,

    What else is on that I2C bus? It looks pretty clearly like something is writing to 0x4C on the deserializer.

    We discussed with OVT yesterday that the vertical blanking was much higher than I was told when filling out the calculator. I believe OVT will be providing updated settings with reduced blanking, let us know if you still see this freeze frame behavior after that.

    Thomas for your reference, here's the saleae log Pratham sent me:

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/138/I2_5F00_REGISTER_5F00_READ.sal

    Regards,

    Katie

  • Hi Pratham,

    Do you have any feedback on the questions from Katie?

    Best,

    Thomas

  • Hello Thomas,

    We have received the new firmware from OVT. Our camera team will flash the firmware and i will  verify it once the process is completed. I will keep you updated on the status.

    Thanks,
    Pratham

  • Hi Pratham,

    Thanks, please let me know if there's any more support needed from our side.

    Best,

    Thomas