Part Number: DP83867IR
Hi,
We are trying to get ethernet working on a custom AM5729-based board.
Our dmesg logs associated with eth/phy/mdio etc. are:
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] arch_timer: cp15 timer(s) running at 6.14MHz (phys).
[ 1.040813] libphy: Fixed MDIO Bus: probed
[ 1.081249] davinci_mdio 48485000.mdio: davinci mdio revision 1.6, bus freq 1000000
[ 1.081261] libphy: 48485000.mdio: probed
[ 1.097189] davinci_mdio 48485000.mdio: phy[0]: device 48485000.mdio:00, driver TI DP83867
[ 1.097788] cpsw 48484000.ethernet: Detected MACID = 20:d7:78:16:84:28
[ 1.097858] cpsw 48484000.ethernet: initialized cpsw ale version 1.4
[ 1.097867] cpsw 48484000.ethernet: ALE Table size 1024
[ 1.097901] cpsw 48484000.ethernet: cpts: overflow check period 1250 (jiffies)
[ 7.611714] net eth0: initializing cpsw version 1.15 (0)
[ 7.665105] TI DP83867 48485000.mdio:00: attached PHY driver [TI DP83867] (mii_bus:phy_addr=48485000.mdio:00, irq=POLL)
[ 7.675516] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[ 7.675527] 8021q: adding VLAN 0 to HW filter on device eth0
Our associated device tree entires:
&davinci_mdio {
// note: compatible entries changed to suit DP83867IRRGZR
phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
&cpsw_emac0 {
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
};
&mac {
slaves = <1>;
status = "okay";
};
We are able to see clock and data signals on MDIO and MDCLK lines. However, we cannot get the eth0 link to be ready.
Any advice would be greatly appreciated.
