Part Number: TLK1221
Hello TI Team,
I am working with the TLK1221EVM and facing an intermittent data alignment issue. I would appreciate your guidance.
My Setup:
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Using TLK1221 in RAW 10-bit mode (SYNCEN = LOW)
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Only TD[2:0] are actively driven
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Remaining TD[9:3] are tied to GND
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PRBSEN = LOW
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RBCMODE = LOW
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Using an external 100 MHz oscillator (50 ppm)
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Clock source and TLK1221 are currently powered from separate power supplies
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Testing internal loopback
Issue Observed:
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Sometimes RD[2:0] match TD[2:0] correctly.
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Other times, after power cycling, the received data appears bit-shifted (misaligned).
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After multiple power cycles, alignment eventually becomes correct.
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Since TLK1221 has no reset pin, full power cycling is required to recover.
Additional Test (Using EVM JMP6):
To rule out low transition density:
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Used JMP6 on EVM
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Drove all TD[9:0] with different data patterns
However:
The same intermittent misalignment is observed.
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