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AM62P-Q1: AM62P-Q1 MDIO interface timing violations

Michele Bisciotti
Prodigy 40 points

Part Number: AM62P-Q1

Hi everybody, 

I am working with the AM62P-Q1 processor, especially on the MDIO interface. I checked the processor MDIO and MDC timings and i found out that the Delay time, MDIO[x]_MDC low to MDIO[x]_MDIO valid timing was violated (the one in the image below, from component datasheet).

image.png

The processor software is currently using the TI driver to drive the MDIO interface. 

I share below the DSO snapshot about the timing violations (the yellow waveform is MDC and the red one is MDIO).

SITARA OUTPUT DELAY TIME.png

Do you have any suggestions to improve this timing situation? Thank you for the support. 

Best regards, 

Michele.

  • 0
    TI__Expert 6830 points

    Hi Michele,

    Thank you for the query !

    From your oscillogram I can see the period of MDC is T = 1.541 uS -> f = 649 kHz. 

    It seems like MDIO interface (MDC max frequency 2.5 MHz) configured to be a bit slow. Is that intentionally ?

    Can you check if you are using a kind of a MDIO manual mode driver (is the MDC generated in software) ?

    Please allow me some time to internally check. I will try to follow-up tomorrow.

    Thanks

    Best Regards,

    Anastas Yordanov

  • 0 in reply to Anastas Yordanov
    Prodigy 40 points

    Hi Anastas, 

    I checked this points with my team.

    In our software we just enable the manual mode without any changes in the driver. By now we are using the PHY C45 protocol for MDIO interface. 

    The frequency value is correct, is about 649 kHz. This value came automatically from the MDIO manual mode driver, so it is not setted intentionally.

    Thanks for the support.

    Best regards, 

    Michele

  • 0 in reply to Michele Bisciotti
    TI__Expert 6830 points

    Hi Michele,

    For the MDIO manual mode driver I can provide the following E2E link, which you can additionally check:

    Notes on 1.5 MHz - 2.5 MHz frequency support by MDIO manual mode driver

    If you look at the example thread clock diagram you can see that the time shift exceeds many times  +-10 ns.  

    I believe that a high frequency + a stable time shift (+-10ns) between the  MDIO and MDC signals when generated in bit-banging mode can be quite challengeable. 

    Moreover in your case I am not sure it is necessary to use the MDIO manual mode driver. As I check the AM62P-Q1 Silicon Errata I can not find any MDIO related advisory notices, and more specifically the i2329 Advisory note for example valid for the Sitara AM62x devices. The typical usage of the manual mode driver is as a workaround of the i2329 issue which seems to be NOT present on AM62P-Q1. 

    Why don't you switch to the classic MDIO "hardware engine" driver and check again the MDC and MDIO signals behavior ?

    Looking forward to your feedback !

    Thanks

    Best Regards

    Anastas Yordanov