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DP83867ERGZ-S-EVM: SGMII bootstrap configuration

William John
Prodigy 10 points

Part Number: DP83867ERGZ-S-EVM

Hi, I'm using the DP83867 SGMII dev board to evaluate replacing using this part to replace a 1G copper SFP module with an FPGA. 

Does the PHY have to be setup over the MDIO interface before it will work in SGMII mode? I can see data coming out of the SO connections and out of my FPGA, but so far as I can tell no data is making it through the PHY to the FPGA, just the 50/BC sync pattern.

  • 0
    TI__Mastermind 33765 points

    Hi William,

    No the PHY does not need to be configured in MDIO to work in SGMII mode. SGMII should be enabled with the default strap configuration on this EVM.

    Can you elaborate on how you connect the EVM to your FPGA? With SGMII being a high speed interface, the connection is sensitive to the transmission medium.

    • Section 2.7.2 of the DP83867 troubleshooting guide shows some basic health checks for SGMII. I'd recommend trying these to see if anything looks off.

    Best,

    Shane

  • 0 in reply to Shane Hauser
    Prodigy 10 points

    Okay thanks, I'll have a look through that guide. 

    I've got the dev board connected to a KC705 dev board through SMA cables. I've previously had my FPGA design working okay through the SFP and have only changed the pinout to the SMA connectors, hence suspect the way the PHY is configured is the problem. 

    I don't think signal integrity is an issue between the boards as I can see in the Xilinx ILA a 0x50 0xBC pattern coming from the PHY, but I never get anything else.  

    I forgot to mention in my original post that I'm trying to use asynchronous SGMII without the CO_P / CO_N connections, is there anything special I need to do for this? I'm assuming they're an output from the dev board and I can't see anything coming out from them. But in the PHY dataset the SGMII_COP is described as "driven by the PHY in SGMII mode" whereas the SGMII_CON is described as "driven by the MAC in SGMII mode", I'm assuming one of these is incorrect? 

  • 0 in reply to William John
    TI__Mastermind 33765 points
    William John said:
    I've previously had my FPGA design working okay through the SFP and have only changed the pinout to the SMA connectors,

    DP83867-S-EVM doesn't have an SFP connection. Can you elaborate on how you got it working through a SFP interface?

    William John said:
    I forgot to mention in my original post that I'm trying to use asynchronous SGMII without the CO_P / CO_N connections, is there anything special I need to do for this?

    The PHY will default to 4-wire SGMII where the clock signals are not used, so you should not need to do anything special to achieve this.

    William John said:
    I'm assuming one of these is incorrect? 

    Yes you are correct. Both COP/N are driven by the PHY so the CON description appears to be incorrect. I'll mark this down for the next revision of the 867 datasheet.

    Best,

    Shane