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TCAN4550: while sending and receiving can data write: No buffer space available issue

Ashwini A
Prodigy 10 points

Part Number: TCAN4550

Two CAN interfaces (can0 and can1) are configured using ECSPI1 and ECSPI3, respectively. Both interfaces are based on the ti,tcan4x5x driver(https://github.com/nxp-imx/linux-imx/blob/lf-6.6.y/drivers/net/can/m_can/tcan4x5x-core.c) , and CAN communication is tested by continuously transmitting data between can0 ↔ can1.

During long-duration CAN traffic testing, the following error is repeatedly observed:
write: No buffer space available

This issue occurs after running the CAN interface for an extended period, while short-duration tests work without any errors.

Below is the device tree configuration used for can0 (similar configuration is used for can1 on ecspi3):
&ecspi1 { /* ECSPI3: TCAN4550 CAN-FD2 */
#address-cells = <1>;
#size-cells = <0>;
fsl,spi-num-chipselects = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
status = "okay";

tcan4x5x1: tcan4x5x@0 {
compatible = "ti,tcan4x5x";
reg = <0>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gpio1>;
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
spi-max-frequency = <18000000>;
bosch,mram-cfg = <0x0 3 2 12 10 0 26 1>;
clocks = <&hclk>, <&cclk>;
clock-names = "hclk", "cclk";
data-ready-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
whether it is related to MRAM configuration, interrupt handling, SPI throughput, or TX queue saturation in the TCAN4550 driver.
Kindly advise on how we should move forward.

  • 0
    TI__Mastermind 35450 points

    Hi Ashwani,

    The issue is SPI throughput.  You are sending CAN messages faster than the processor can read and clear the RX buffers and this eventually leads to a RX FIFO Full or Overflow condition.

    You will essentially need to determine the overall amount of time needed by your processor to detect a new message has arrived through an interrupt or SPI register reads, determine the RX FIFO buffer used for the message and calculate the starting address for the buffer, read the message contents from the buffer, and then acknowledge the buffer has been read and clear the interrupt through SPI writes.  

    The SPI interface will be a limiting factor to the maximum CAN message throughput.  Increasing the number of RX FIFO Buffer elements can help alleviate short intervals of increased message reception because it allows these messages to be held in memory until the MCU can read them.  However, for prolonged message reception at a rate faster than the time required to process the message will eventually lead to an overflow and the CAN message data will be lost.

    Regards,

    Jonathan