Part Number: DS90LVRA2-Q1
Hi,
I am using this part on high speed ADC interface signals going into an FPGA (at 2.5V). We are extremely tight on timing with the +/-300psec channel-to-channel skew variation. We aren't as concerned with the actual skew itself (which we can compensate for) but rather the variation in potential skew. We will operate very near 2.5V with temperatures realistically between 0-75C. So I have two questions:
- Given our temperature range, is there anything that would allow us to assume a smaller skew variation? I'm just wondering how likely it is we actually see +/-300psec channel-to-channel.
- On a given part, do you have any data on how much skew variation there could be over the lifetime? We are looking at calibrating for the channel-to-channel skew, but this would require some evidence that a given part won't drift over days of runtime to either extreme.
