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TCAN1145EVM: Normal mode of TCAN1145‑Q1

Part Number: TCAN1145EVM
Other Parts Discussed in Thread: TCAN1145-Q1

We are using the TCAN1145-Q1 in our project and have observed a reproducible behavior during testing that appears to be related to the device’s power thresholds and internal state machine. Specifically, when Vcc is briefly pulled to 0 V (intentionally creating an UVcc condition) while Vsup remains present, whether the device can be switched to Normal mode via SPI immediately afterward depends on whether Vsup drops below the recovery / power-on threshold (Uv_sup) during this process.

We have reviewed the publicly available datasheet, but we are still unable to determine the exact cause behind this behavior, especially regarding the following questions:

  • What is the internal difference in device state between:
    1. Vcc drops but Vsup does not fall below its threshold, and
    2. Vcc drops and Vsup also falls below its threshold?
  • In the case where Vcc drops but Vsup does not fall below its threshold, why is the device unable to switch to Normal mode via SPI, even though writes and readbacks to the MODE_CNTRL register are successful?
  • In the case where Vcc drops and Vsup falls below the threshold and then recovers, why can the same SPI command to switch to Normal mode take effect immediately after Vcc is restored, even though the register behavior is identical to the previous case?
  • Is there any internal state machine protection logic or fault latch mechanism not explicitly described in the datasheet that could explain the behavior?

We kindly request your assistance in confirming whether the above observations are consistent with the intended device design and to provide further technical clarification.


Test Environment

  • Device: TCAN1145
  • Power and interfaces:
    • Vsup: Lab power supply, nominal 12 V (pulled down & restored per test steps)
    • Vcc: 5 V LDO, includes intentional drop to 0 V and recovery
    • Vio: MCU 3.3 V IO rail
  • SPI Host: TC332, CLK = 2.4 MHz

Two test sequences with different outcomes

A) Vsup pulled down to 3.8 V and then raised to 8 V → Able to switch to Normal immediately

(Refer to attachment: 3.84v_ok.png)

  1. Initial state: Normal mode (VSUP=12 V, VCC=5 V, VIO=3.3 V, transceiver=Normal).
  2. Pull VCC to 0 V (create UVcc).
  3. Pull VSUP down to 3.8 V, then lift to 8 V — this appears to trigger a “fast power-on/Standby transition.”
  4. Write MODE_SEL = Normal via SPI; register write and readback both successful.
  5. Restore VCC to 5 V → the device immediately enters Normal mode when UVcc clears.

B) Vsup pulled down only to 4.58 V, then raised to 10 V → Immediate Normal-mode switching fails

(Refer to attachment: 4.58v_KeepSleep.png)

  1. Initial state: Normal mode (VSUP=12 V, VCC=5 V, VIO=3.3 V, transceiver=Normal).
  2. Pull VCC to 0 V (create UVcc).
  3. Pull VSUP to 4.58 V, then raise to 10 V.
  4. Write MODE_SEL = Normal via SPI; register write and readback are successful.
  5. Restore VCC to 5 V → transceiver remains in Sleep mode and does not communicate.
  6. Writing MODE_SEL = Normal again transitions the device to Normal mode, and communication works normally.
  • Hi Yujuan,

    Thanks for reaching out on E2E!

    In general, I would recommend reviewing the state diagram in Figure 10-8 and the UVCC diagram in Figure 10-23 in the datasheet. Also I am not seeing your attachments. If they still don't work, I would recommend inserting them into a powerpoint document and uploading that. 

    However, you have found a niche behavior that is not explicitly documented in the datasheet. VCC must be supplied at least once in order for the VCC undervoltage flag to be raised. It seem like you are running into this issue.

    Test A:

    • This VSUP voltage is considered an undervoltage condition, and it has essentially rebooted the transceiver. The UVCC undervoltage flag is not raised because VCC has never been supplied yet. Once VCC is present, it is actually able to enter Normal mode automatically. 

    Test B:

    • VSUP never drops below the undervoltage threshold. It is always powered on in this scenario.
    • Since VCC was previously enabled, and now VCC is removed, the VCC undervoltage flag is now raised. 
      • This causes the transceiver to enter Sleep mode.
    • Since VIO is still supplied, the transceiver properly receives the SPI write to enter Normal mode.
      • But because the UVCC flag is raised, it ignores this mode transition.
    • Once the UVCC flag is removed, the transceiver properly can switch into Normal mode.

    This is somewhat confusing so let me know if that makes sense. But overall, this transceiver is operating correctly. 

    Best,

    Ethan

  • In Test A, after VBAT is powered on at 10 V, VCC is applied with a delay of 0.2 seconds. Why is the UVCC flag not set in this case?
  • Hi Yujuan,

    I explained this in my first post. Since the VBAT voltage shown in your waveform drops below 4.25V (it seems to be 3.8V in your waveform), the transceiver considers this to be a restart condition. The UVCC flag will only trigger after the VCC supply has been supplied before. The prior VCC supply is not considered since the transceiver restarted. 

    Best,

    Ethan