PCA9518: I2C failure on back to back read/write transactions

Shubham Srivastava

Part Number: PCA9518
Other Parts Discussed in Thread: TCA9406, TXS0102, TCA9416

Hi Team,

We are facing issues with back to back read/write transactions through the HUB.

This is only encountered when we do this through a test script. If a dealy of 300ms is added between read/write it works fine.

Also, there is no issue observed if we do manual read/write back to back through command line.

Please advise.

Best Regards,

Shubham

9 days ago

0 Clemens Ladisch 8 days ago

Guru 320600 points

What is that issue?

Please show an oscilloscope trace of the signals on both sides of the hub.

0 Joshua Salinas 8 days ago

TI__Mastermind 31580 points

Hello Shubham,

Our Apps team is current out of office because of a US holiday. Please expect delays in our response. Thank you for your understanding.

Regards,

Josh

0 Tyler Townsend 7 days ago

TI__Guru 56358 points

Hi Shubham,

I agree with Clemens here.

A scope capture would be helpful to understand how the I2C waveforms look before and after the hub.

Regards,

Tyler

0 Shubham Srivastava 5 days ago in reply to Tyler Townsend

Prodigy 50 points

Hi Clemens & Tyler,

PFA of scope captures.

This is done for the periodic transaction.

Best Regards,

Shubham

0 Tyler Townsend 5 days ago in reply to Shubham Srivastava

TI__Guru 56358 points

Hi Shubham,

I am not noticing anything significant on the waveforms.

What is the target device you are communicating with?

Why choose a delay of 300ms?

Does 1 ms work the same as 300ms between a write and read command? I am trying to understand if it is timing related.

Regards,

Tyler

0 Shubham Srivastava 4 days ago in reply to Tyler Townsend

Prodigy 50 points

Hi Tyler,

The target device is a Lattice CPLD LCMXO3LF-9400C-5BG400CAK7.

We started trials with 1s and came down to 300ms with pass transactions, it fails at 200ms.

The status byte on master side (FPGA) shows BUS-hung | SCL-High | SDA Low, whenever we have a failure.

Also, we saw an errata for this part w.r.t Clock Stretching. Can this be any where related to our issue.

Best Regards,

Shubham

0 Tyler Townsend 4 days ago in reply to Shubham Srivastava

TI__Guru 56358 points

Hi Shubham,

Is there clock stretching when talking to the CPLD?

The clock stretching errata is more associated with any device that uses rise-time accelerators in the system. Are there RTA's in your system? Devices such as TCA9416 / TCA9406 / TXS0102.

The clock waveform looks okay, but can you zoom in on a single clock pulse to verify that it is clean? It looks like there might be more information to see on the rising edge.