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TLK10232: TX_FIFO_UNDERFLOW and RX_FIFO_UNDERFLOW

Part Number: TLK10232

Hello,

I have a board with TLK10232 connected to CX4 connector for XAUI transfer on the LS side and to SFP+ on the HS side.

I'm using BIDI SFP+.

I connect two boards together using the optical link and perform electrical loopback on the XAUI interface.

I configured the TLK10232 as follows using the "low level configuration" option in the GUI:

  1. Reset device (write a 1 to 0x1E.0000 bit 15 or assert RESET_N pin)
  2. Make sure the reference clock selection (156.25 MHz or 312.5 MHz) is correct – this is done through register 0x1E.001D bit 12 (default is 156.25 MHz)
  3. Disable auto-negotiation by writing 1’b0 to 0x07.0000 bit 12
  4. Disable link training by writing 16’h0000 to 0x01.0096
  5. Write 16’h03FF to 0x1E.8020.  This allows the link settings that would normally be configured through KR training to be configured manually instead.
  6. Depending on the link conditions, you may need to change the default configuration of 0x1E.0003 and 0x1E.0004.  For optical connections, we typically recommend changing HS_ENTRACK (0x1E.0004 bit 15) to 1’b1 and HS_EQPRE (0x1E.0004 bits 14:12) to 3’b101.  This can be a starting point, but you may need to do some BER testing to optimize the values.
  7. Issue a data path reset by writing 1’b1 to 0x1E.000E bit 3.

The link is established ok.
After few minutes to an hour I see that one board reports TX_FIFO_UNDERFLOW (0x1E.000F bit 7) while the mate board report RX_FIFO_OVERFLOW (0x1E.000F bit 4). And TX_FAULT (0x1.0008 bit 11)

In some cases, it is TX_FIFO_ OVERFLOW on one board and RX_FIFO_ UNDERFLOW on the mate.

The problem is that failure persists. The bits do not clean after reading. It clears only after I perform data path reset by writing 1’b1 to 0x1E.000E bit 3.

The problem occurs only with BIDI SFP+ units, while on duplex SFP+ it doesn’t happen.
When checking PRBS errors on the HS side I see errors on the BIDI SFPs but no errors on the duplex SFP+. BTW the XAUI interfaces are always error free.

On one hand the problem is clearly the SFP+ BIDI problem, on the other hand the SFP+ BIDI BER is  ~6.7e-14 (checked over 24 hours with the PRBS test) which is better than the industry standard of 1e-12. And I’m afraid that it will happen with other SFP+ modules

Is there a way recover from the FIFO failure without data path reset?

When performing data path reset during normal operation there is lots of traffic loss.

 

Regards,

Yossi