SN65DSI84-Q1: TFT LVDS module (1280 (W) x RGB x 800 (H)) compatibility

Hi Vanlentin,

To find whether this resolution can be supported, we would use the LVDS pixel clock rate. 

LVDS PCLK rate = Horizontal total (pixels) x Vertical total (lines) x frame rate (fps).

To get the exact PCLK, we would need these values totals and frame rate.

Estimate:
However, if we assume, a 15% blanking overhead and 60fps, then the PCLK = ((1280 x 800) x 115%) x 60 fps = 70.656 MHz, which is within the LVDS CLK limits.
Note that since the blanking and frame rate are assumed, this is not exact. To get exact resolution, we would need more information.


Resolution guide:
The DSI84 supports dual LVDS outputs with both ports supporting 25 - 154 MHz.
For reference: [FAQ] SN65DSI84: SN65DSI83, SN65DSI84, and SN65DSI85 resolution guide

The DSI84 can support 8 bit LVDS/ 24bpp.

Best regards,
Ikram

Hi Ikram, 

Thank you for your comment. Below you will find additional information from my TFT's technical specifications:

PCLK = DCLK = 72.4MHz (typical) 

...

If I understand correctly, the SN65DSI84-Q1 can handle my LVDS TFT module. Can I send you the screen pinout to check if we can connect the two together?

Best regards, 

Valentin 

Hi Valentin,

The 72.4 MHz PCLK rate you shared is supported by the DSI84, since it is within the 25 - 154 MHz per port limit.


The DSI84 supports LVDS output with two ports, each with one clock lane and four data lanes. It can support 18 or 24 bpp color depths. You can share the pinouts here too.

Best regards,
Ikram

HI Ikram, 

Thank you for these details, it seems perfect for my design.

Please find attached the technical data sheet for the TFT module we would like to use.

Thank you in advance for double-checking and reviewing this. I am very confident about using the DSI84 for my project.

Please let me know if I have missed anything regarding the specifications of our TFT module. 

Best regards, 

Valentin 

13-101ZIEBCAD0-S.pdf