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DP83826AE: DP83826AE ECAT PCB guidelines

Sanath Hoysala
Prodigy 30 points

Part Number: DP83826AE

Hi team,

I am using an XMC4800 to interface DP83826AE PHY for ECAT communication. I have the following signals coming from the XMC4800 ESC(ethercat slave controller) to PHY.

  1. TXD[0:3], TXEN and TXCLK
  2. RXD[0:3], RXERR, RXDV and RXCLK

The above signals are coming for both the PHY's individually and the common signals for the two PHY's are:

  1. MCLK, MDIO
  2. 25MHz clock IN to XI pin on PHY from ESC clockout pin

Can you please provide the design guidelines as follows:

  1. Can you please provide the length matching and impedance matching details for each signal where applicable.
  2. What are the length matching groups we need to make in these signals ?
  3. If applicable, what are the group-to-group length matching constraints?
  4. What are the constraints or rules for routing the 25MHz clock from XMC to PHY? 

Thank You

Sanath

  • 0
    TI__Mastermind 35735 points

    Hi Sanath,

    1. I recommend length matching all MII RX signals to within 20mils and all MII TX signals to within 20mils where possible. All MII traces should be routed at 50 ohm impedance. MDIO and MDC have no length/impedance matching requirements.

    2. All MII RX signals (RXD[0:3], RXCLK,...) would be one length matching group and all MII TX signals (TXD[0:3], TXCLK,...) would be the other.

    3. While there are no group to group (RX to TX) length matching constraints, all MII traces should be 6 inches or shorter for best performance. Additionally vias should be kept to a minimum on MII traces.

    4. The 25MHz clock trace should be as short as possible and surrounded by GND planes to minimize emissions. You may consider using GND fill on the sides of the clock trace or embedding this trace between GND planes of the board.

    Best,

    Shane