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ADC34RF72EVM: ADC clock input questions – ADC34RF72EVM

seungpum kang
Prodigy 190 points

Part Number: ADC34RF72EVM
Other Parts Discussed in Thread: LMK04828

Hello,

I have two questions regarding the ADC34RF72EVM.

  1. The user guide (SLVUDB9) states that the ADC clock input at J5 should be driven at 9 dBm.

    • If the input clock power is lower than 9 dBm, does this cause measurable ADC performance degradation (e.g. SNR / ENOB)?

    • Is 9 dBm a strict requirement or a recommended level with margin?image.png

  2. Is the ADC34RF72EVM intended to be clocked directly from an external signal generator?

    • Since the board includes an LMK04828, can the ADC be fully clocked using the LMK04828 output without an external clock source?

    • If so, what is the intended use of the external clock input (J5)?

Best regards,
Seungbeom Kang

  • +1
    TI__Mastermind 45670 points

    HI Seungbeom,

    1) - no, using a +9 or +10dBm increases the slew of the clocking edge and actually increase SNR/ENOB performance. We also typically assume the customer will follow the use guide and use a sig gen and bandpass filter, which will reduce the signal swing that eventually gets to the ADC clocking pins.

    2) - yes, clocking directly from a sig gen is best. The LMK is used to derive the refclk for the FPGA.

    Regards,

    Rob