Part Number: DP83640T-EVK
Other Parts Discussed in Thread: DP83640
Hi ,
I am working with FPGA's for Digital substation applications where we have been trying to reach the final step of time synchronising with the external PtP server clock.
Our fpga is not capable of hardware timestamping . So I took the decision of using an external PHY which is capable of it . For now I have been successful in configuring the gpio to give out a pps pulse( But its synchronised with the PHY's time base) .
I have also successfully connected the external PHY for duplex communication using my FPGA board . where i am able to recieve and send the UDP packets . I have done for SV packets too .
Now I am trying to get the answer that how i am looking to implement the stack is I recieve the ptp packet through this PHY and also the recieve timestamp . then send back the delay_req and see delay_resp . I get all 4 times and then i write to the PHY clock using mdio this clock offset so it corrects itself .
Is this way of thinking correct ? Is there an easier way of implementing it ?
Implementing using a Linux driver is not an option . We are going bare metal .
Thanks for any help or guidance.
